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[209.132.180.67]) by mx.google.com with ESMTP id 15-v6si14946870pla.23.2018.01.31.10.40.37; Wed, 31 Jan 2018 10:40:52 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BM1MLj+R; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751608AbeAaSkN (ORCPT + 99 others); Wed, 31 Jan 2018 13:40:13 -0500 Received: from mail-wm0-f47.google.com ([74.125.82.47]:56169 "EHLO mail-wm0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751296AbeAaSkL (ORCPT ); Wed, 31 Jan 2018 13:40:11 -0500 Received: by mail-wm0-f47.google.com with SMTP id 143so990866wma.5 for ; Wed, 31 Jan 2018 10:40:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:subject:to:cc:references:message-id:date:mime-version :in-reply-to:content-language:content-transfer-encoding; bh=I+oNiJJVzNqljVWRezA3VueOoVa/HqFEWjQ4oRMNfe4=; b=BM1MLj+RuT0HeHlLlmPGs3bXL3xFyvppeUnF21QbviwBWhqdqXvbryOUaFzp8/Y9FM h2RhgSaL8zkCb94hywQDFxYIvibNlwvJp9geu4v8hdi91c356BcYvqCQ8N1TFiMGsLzv AUHMdd091sAvM3ZwfQhm4KaeycH0fN1ZyzaTQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:subject:to:cc:references:message-id:date :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=I+oNiJJVzNqljVWRezA3VueOoVa/HqFEWjQ4oRMNfe4=; b=oN8IZTr2hiTtT75TsoG8l3kAv3MFmqwM80sCYlS28JudxnW7V4DrLWroVGi8ZT5p6w QsK+S38v4j2keeYhzx2qT9j/L+7oOcWM7mHBni5EROXzOfDAEe2C7sQwo/cQ9DvNDqVs l6cLD0RFlkaDR3vAqKpiNbEdI35+9nRUuIhrdveLoe/evNZywiytrkV73YWkM8QoSXNs HA7PqQ/zr2buSDZKYEXj5Hjv4qUDxqx+nJw2KtoWHX2MI3MokHpnjDWkR3PKqUkJe3u7 C85XjIykyfSU3UzKCWHRZ2IcPbut3xYgp+ge6TvUVHQIfIPy5oHO2fBZI2ngZmdvLAxy PONA== X-Gm-Message-State: AKwxytcQM++snozhVyEVHniC2q0Ec7EQpQBkSktttl94RHYne6EygXh2 jxpd5R9JJSbx6frn85ug8m3DiA== X-Received: by 10.28.124.25 with SMTP id x25mr2547638wmc.49.1517424009934; Wed, 31 Jan 2018 10:40:09 -0800 (PST) Received: from [10.44.66.8] ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id k7sm17550717wrg.38.2018.01.31.10.40.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Jan 2018 10:40:08 -0800 (PST) From: Georgi Djakov Subject: Re: [PATCH v11 2/6] mailbox: qcom: Create APCS child device for clock controller To: Jassi Brar Cc: Bjorn Andersson , Stephen Boyd , Michael Turquette , Rob Herring , linux-clk@vger.kernel.org, Linux Kernel Mailing List , linux-arm-msm@vger.kernel.org, Devicetree List References: <20171205154701.27730-1-georgi.djakov@linaro.org> <20171205154701.27730-3-georgi.djakov@linaro.org> <20171224050625.GH12655@minitux> Message-ID: <549f02e5-19d7-8cec-674f-247dfb2d2467@linaro.org> Date: Wed, 31 Jan 2018 20:40:07 +0200 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jassi, On 01/27/2018 05:44 AM, Jassi Brar wrote: > On Thu, Jan 4, 2018 at 10:26 PM, Georgi Djakov wrote: >> Hi Jassi, >> >> On 12/29/2017 08:14 AM, Jassi Brar wrote: >>> Hi Bjorn, >>> >>> On Sun, Dec 24, 2017 at 10:36 AM, Bjorn Andersson >>> wrote: >>>> On Fri 22 Dec 20:57 PST 2017, Jassi Brar wrote: >>>> >>>>> On Tue, Dec 5, 2017 at 9:16 PM, Georgi Djakov wrote: >>>>>> There is a clock controller functionality provided by the APCS hardware >>>>>> block of msm8916 devices. The device-tree would represent an APCS node >>>>>> with both mailbox and clock provider properties. >>>>>> >>>>> The spec might depict a 'clock' box and 'mailbox' box inside the >>>>> bigger APCS box. However, from the code I see in this patchset, they >>>>> are orthogonal and can & should be represented as independent DT >>>>> nodes. >>>> >>>> The APCS consists of a number of different hardware blocks, one of them >>>> being the "APCS global" block, which is what this node and drivers >>>> relate to. On 8916 this contains both the IPC register and clock >>>> control. But it's still just one block according to the hardware >>>> specification. >>>> >>>> As such DT should describe the one hardware block by one node IMHO. >>>> >>> In my even humbler opinion, DT should describe a h/w functional unit >>> which _could_ be seen as a standalone component. >> >> The APCS is one separate register block related to the CPU cluster. I >> haven't seen any strict guidelines for such cases in the DT docs, and >> during the discussion got the impression that this is the preferred >> binding. Rob has also reviewed the binding, so we should be fine to move >> forward with this one. >> > Well, I can't overrule Rob. But I am really not happy with random > device spawning from mailbox drivers. I know there are such instances > already in the kernel but that doesn't make it legit... unless there > is some hard dependency. Is there? The dependency is that on this SoC, these functionalities are combined into this "CPU subsystem" block. Initially APCS was a syscon and it was discussed it an year ago in this mail thread [1] and we are trying to move away from the syscon and come up with some bindings. During v8 and v9 of this patchset i have switched from multiple child nodes to a single node as this seem to be the preferred form. >>> For example, if this APCS had a mac controller, would we also populate >>> a netdev from mailbox driver? And what if next revision moves/drops >>> this clock controller out of APCS, keeping mailbox controller exactly >>> same? >> >> The clock controller may change in some next SoC architecture and that's >> why the SoC version is also part of the the compatible string. >> > So the mailbox driver will be updated to spawn yet another type of clock? > And again for next revision and so on... I know that is unlikely but > the point is why not have separate clock drivers for independent h/w > clocks? Each revision re-shuffles the APCS block, so at least the offsets would be different. I don't see anything bad with spawning a child device, but what are the other options? Should we go back on the bindings and suggest something new all over again? Or do you have any other idea? Could you please explain your point further? Thanks, Georgi [1] https://lkml.org/lkml/2017/3/20/991