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From:   Jim Mattson <jmattson@google.com>
Date:   Wed, 31 Jan 2018 11:45:50 -0800
Message-ID: <CALMp9eTNyjrQLViYkopsHp57saQwjNRnMTJt_pZVsaFvaUS9tQ@mail.gmail.com>
Subject: Re: [PATCH v5 2/5] KVM: x86: Add IBPB support
To:     KarimAllah Ahmed <karahmed@amazon.de>
Cc:     kvm list <kvm@vger.kernel.org>,
        LKML <linux-kernel@vger.kernel.org>,
        "the arch/x86 maintainers" <x86@kernel.org>,
        Ashok Raj <ashok.raj@intel.com>,
        Asit Mallick <asit.k.mallick@intel.com>,
        Dave Hansen <dave.hansen@intel.com>,
        Arjan Van De Ven <arjan.van.de.ven@intel.com>,
        Tim Chen <tim.c.chen@linux.intel.com>,
        Linus Torvalds <torvalds@linux-foundation.org>,
        Andrea Arcangeli <aarcange@redhat.com>,
        Andi Kleen <ak@linux.intel.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Dan Williams <dan.j.williams@intel.com>,
        Jun Nakajima <jun.nakajima@intel.com>,
        Andy Lutomirski <luto@kernel.org>,
        Greg KH <gregkh@linuxfoundation.org>,
        Paolo Bonzini <pbonzini@redhat.com>,
        Peter Zijlstra <peterz@infradead.org>,
        David Woodhouse <dwmw@amazon.co.uk>
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On Wed, Jan 31, 2018 at 11:37 AM, KarimAllah Ahmed <karahmed@amazon.de> wrote:

> +       nested_vmx_disable_intercept_for_msr(msr_bitmap_l1, msr_bitmap_l0,
> +                                            MSR_IA32_PRED_CMD,
> +                                            MSR_TYPE_W);
> +

I still think this should be predicated on L1 having
guest_cpuid_has(vcpu, X86_FEATURE_IBPB) or guest_cpuid_has(vcpu,
X86_FEATURE_SPEC_CTRL), because of the potential impact to the
hypertwin. If L0 denies the feature to L1 by clearing those CPUID
bits, L1 shouldn't be able to bypass that restriction by launching L2.