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Subject: Re: [PATCH] x86: Align TLB invalidation info
From:   Nadav Amit <nadav.amit@gmail.com>
In-Reply-To: <CALCETrX-zmhoLgZzL_VJZqZF+XTS26o+HHA7=vA+E7T88yO_uA@mail.gmail.com>
Date:   Wed, 31 Jan 2018 13:17:36 -0800
Cc:     Dave Hansen <dave.hansen@linux.intel.com>,
        the arch/x86 maintainers <x86@kernel.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Ingo Molnar <mingo@redhat.com>,
        "H. Peter Anvin" <hpa@zytor.com>,
        LKML <linux-kernel@vger.kernel.org>,
        Peter Zijlstra <peterz@infradead.org>
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References: <20180131201118.1694-1-namit@vmware.com>
 <8bb352bc-4e1f-4e87-80e3-a8e65d618d2a@linux.intel.com>
 <0E65629C-0D7D-4602-A43D-B18E62F330A6@gmail.com>
 <CALCETrX-zmhoLgZzL_VJZqZF+XTS26o+HHA7=vA+E7T88yO_uA@mail.gmail.com>
To:     Andy Lutomirski <luto@kernel.org>
Sender: linux-kernel-owner@vger.kernel.org
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Andy Lutomirski <luto@kernel.org> wrote:

> On Wed, Jan 31, 2018 at 1:09 PM, Nadav Amit <nadav.amit@gmail.com> =
wrote:
>> Dave Hansen <dave.hansen@linux.intel.com> wrote:
>>=20
>>> On 01/31/2018 12:11 PM, Nadav Amit wrote:
>>>> The TLB invalidation info is allocated on the stack, which might =
cause
>>>> it to be unaligned. Since this information may be transferred to
>>>> different cores for TLB shootdown, this might result in an =
additional
>>>> cache-line bouncing between the cores.
>>>>=20
>>>> GCC provides a way to deal with it by using
>>>> __builtin_alloca_with_align(). Use it to avoid the bouncing cache =
lines.
>>>=20
>>> It doesn't really *bounce*, though, does it?  I don't see any writes =
on
>>> the remote side.  The remote use seems entirely read-only.
>>>=20
>>> You also don't have to exhaustively test this, but I'd love to see =
at
>>> least a sanity check with a microbenchmark (or something) that, yes,
>>> this does help *something*.  Maybe it makes the remote
>>> flush_tlb_func_common() run faster because it's pulling in fewer =
lines,
>>> or maybe you can even detect fewer misses in there.
>>=20
>> I agree that with the whole Meltdown/Spectre entry-cost it might not =
even be
>> measurable, at least on small ( < 2 sockets) machines. But I do not =
think it
>> worth profiling. Basically, AFAIK, all the data structures that are =
used for
>> inter-processor communication by the kernel are aligned, and this is =
an
>> exception.
>=20
> This is only going to be measurable at all on NUMA, I suspect.

Yes, I meant <=3D 2 ...=20