Received: by 10.223.176.5 with SMTP id f5csp1915292wra; Wed, 31 Jan 2018 13:36:44 -0800 (PST) X-Google-Smtp-Source: AH8x224paNu7ESFOiqhtU9JCKm4ReWmH1vTwjYuOvrL7GnTcVZN+7w4mj1dflGrKJNW4cUnhX9GZ X-Received: by 10.99.111.68 with SMTP id k65mr27531359pgc.446.1517434604648; Wed, 31 Jan 2018 13:36:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517434604; cv=none; d=google.com; s=arc-20160816; b=dC84waFOiAEnjFmW06eSNJLD0K2/HUsqT9Lq0QXz/q3WRjgBFX2+e8Mir+fs6wHpgS t4ZlTn6fQLdzB7VN+ut7GL+7+6aq58/IBdkw0Cvb9Rkdq9hDAfQVQvNNvj2466C9kDfY OPxw+3x4ovXsSz2yZWF18m8PLtPj3IiA6YVS6YkOorqpXihOWxNQFPMtG/Amj3CIAAe6 RuBd65VgbLNGFVrAMh9h3bG5fXhWLxREMnkS6dyflNkBIcn7fAn7eYRHdFWH5pnXWGHv ROJk9wzW7W8CBcR8HRO4Vv/fNyLuXsZqI0JLwyw2Sgd1fVAa/m1mrHQw2ICsJb9p5FVi 70dQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=it7EQ+CRq7niaUDscsG+WLADZDXjKPX4fuZKxm//Jjs=; b=A2Da+a/QP4lOG4BUrgyNhhbfmB4kNU/VOGhPl2nAZoEGWTkBrFZw8qhsPJ4Lzh6+Dq mgixbIq4jUcQHOJjjW4A5uENpFJVpw0EHj0cPwlJ3qp2tR44cy+zfElGut+p2rfXZuQm Qbzg6jYqHKq4c4Wkne1UzxLG+w7tPbeGwXox536OYy9ZggxqRkF+mh5bPWkqJyHVGUIi RXD8Ov5eLQhvcyJeYd0F5DJo95EK7PXkQYo4pcyGXEH2dXR6OhIatKuG+Hq7Zr1N6EMH psWlAfKBqRVbOntFWhTkSQz7B9D1zn4ehIG65xQVeoWlc8AkiVHecLVMPMxpRH2qO7om p2dg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=bv/NN8Qr; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o2-v6si624893pll.718.2018.01.31.13.36.28; Wed, 31 Jan 2018 13:36:44 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=bv/NN8Qr; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753253AbeAaVf7 (ORCPT + 99 others); Wed, 31 Jan 2018 16:35:59 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:55978 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753154AbeAaVf5 (ORCPT ); Wed, 31 Jan 2018 16:35:57 -0500 Received: by mail-wm0-f66.google.com with SMTP id 143so1860374wma.5; Wed, 31 Jan 2018 13:35:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=it7EQ+CRq7niaUDscsG+WLADZDXjKPX4fuZKxm//Jjs=; b=bv/NN8QrS5xs8fOaYiWtqx2DZevH79ErTZvSz8dMxL2L1jndPeog0GQtYacIj/7Hg8 e2A6mNHFOBlPVoZmzwdH8E8Ac2bzH5z2Z99Y5hR3QxqrhWLa0YAUx2d1ERkGWdnXKNSm vH27KRhMTY/J+Ebe/JC+1ColYgUufWpsmTZT6T3dexLaSVjtYguUKdV4pVc/ZaWjKgMA UNRXp/JsFDfPTvbcECgDyCuNiMEENp/JqsCitlAxDNv0jA1DJy7smqg4/MPbZpuvkrHy 9gEliwanrKXECAXbLyGDajcnUuq4ClflSnrdLr9G4U95rTgR+eZxdZUZLdE+dgTlIAvA t4xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=it7EQ+CRq7niaUDscsG+WLADZDXjKPX4fuZKxm//Jjs=; b=EN6CzqAG0xXE9aWjhUe5RtnBSHDdYy2B0rWds5qvupjaDaY0eKi7iawwCmAo7fuTyx Nmowc4ua4YPSPS9pzVOEBMItgMl8zlq/M04G0S86J27LHtSu7xmYlFDsCLoczJFjWgfk mBdu1Bs2twJAE+aOo6dzQMhjWB5sfv6S0sURqvc8blPW1Mf11ZUpYGKNiznaAOyTqWx9 RV0Iu/w8ysdLtRw5KPkZDsbUl8xeymeD8CdjPXS4fWoKlf2nBCAUoqMwg2ZXqBT6tlGy DXkFAKVJxSz9bK9y1F3HlTR95mR9Xzxzt1e7P43orVVHpg2CWF5WmotyOWEFr7rLgB62 C+0A== X-Gm-Message-State: AKwxytcyhtzkPz5vGEmvPHwJlOpdMqcuHv/5otdDn8KQ3K5QG6bgwt24 hFvs5Nuu5ZnXH3LuWLiw6V9cAywA X-Received: by 10.28.203.135 with SMTP id b129mr23266824wmg.155.1517434555516; Wed, 31 Jan 2018 13:35:55 -0800 (PST) Received: from localhost.localdomain (vno44-1-88-172-188-148.fbx.proxad.net. [88.172.188.148]) by smtp.gmail.com with ESMTPSA id s19sm18197538wrg.7.2018.01.31.13.35.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Jan 2018 13:35:54 -0800 (PST) From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Russell King , Mark Rutland , Rob Herring , Fabio Estevam , Sascha Hauer , Shawn Guo Cc: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Michael Nazzareno Trimarchi , =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Subject: [PATCH v3 1/2] ARM: dts: imx25-pinfunc: Use consistent naming for eSDHC Date: Wed, 31 Jan 2018 22:35:43 +0100 Message-Id: <20180131213544.4508-1-benoit.thebaudeau.dev@gmail.com> X-Mailer: git-send-email 2.14.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This file had several naming inconsistencies for eSDHC: - the instances were named sometimes SDn, sometimes SDHCn, whereas they are named ESDHCn in the reference manual, e.g.: MX25_PAD_SD1_CMD__SD1_CMD MX25_PAD_D15__SDHC1_DAT7 - the data ports were named sometimes DATAn, sometimes DATn like in the reference manual, e.g.: MX25_PAD_SD1_DATA0__SD1_DATA0 MX25_PAD_D15__SDHC1_DAT7 - in one case, the clock port was named DAT_CLK instead of CLK: MX25_PAD_CSI_D7__SDHC2_DAT_CLK This change: - introduces new definitions using the naming from the reference manual, - keeps definitions using the legacy naming in order not to break compatibility for out-of-tree users (they can be removed later), - updates the in-tree files that were using the legacy naming. Cc: Uwe Kleine-König Signed-off-by: Benoît Thébaudeau Acked-by: Uwe Kleine-König --- Changes v2 -> v3: - None. Changes v1 -> v2: - New patch (suggested by Uwe). --- .../boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts | 12 ++-- arch/arm/boot/dts/imx25-pdk.dts | 12 ++-- arch/arm/boot/dts/imx25-pinfunc.h | 72 ++++++++++++++-------- 3 files changed, 60 insertions(+), 36 deletions(-) diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts index 0f053721d80f..6273a1f243ed 100644 --- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts +++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts @@ -88,12 +88,12 @@ pinctrl_esdhc1: esdhc1grp { fsl,pins = < - MX25_PAD_SD1_CMD__SD1_CMD 0x400000c0 - MX25_PAD_SD1_CLK__SD1_CLK 0x400000c0 - MX25_PAD_SD1_DATA0__SD1_DATA0 0x400000c0 - MX25_PAD_SD1_DATA1__SD1_DATA1 0x400000c0 - MX25_PAD_SD1_DATA2__SD1_DATA2 0x400000c0 - MX25_PAD_SD1_DATA3__SD1_DATA3 0x400000c0 + MX25_PAD_SD1_CMD__ESDHC1_CMD 0x400000c0 + MX25_PAD_SD1_CLK__ESDHC1_CLK 0x400000c0 + MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x400000c0 + MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x400000c0 + MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x400000c0 + MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x400000c0 >; }; diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index 2d15ce72d006..498496deaa27 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts @@ -165,12 +165,12 @@ pinctrl_esdhc1: esdhc1grp { fsl,pins = < - MX25_PAD_SD1_CMD__SD1_CMD 0x80000000 - MX25_PAD_SD1_CLK__SD1_CLK 0x80000000 - MX25_PAD_SD1_DATA0__SD1_DATA0 0x80000000 - MX25_PAD_SD1_DATA1__SD1_DATA1 0x80000000 - MX25_PAD_SD1_DATA2__SD1_DATA2 0x80000000 - MX25_PAD_SD1_DATA3__SD1_DATA3 0x80000000 + MX25_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 + MX25_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 + MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 + MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 + MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 + MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 MX25_PAD_A14__GPIO_2_0 0x80000000 MX25_PAD_A15__GPIO_2_1 0x80000000 >; diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h index 6c63dca1b9b8..2915c65a13c9 100644 --- a/arch/arm/boot/dts/imx25-pinfunc.h +++ b/arch/arm/boot/dts/imx25-pinfunc.h @@ -151,21 +151,21 @@ #define MX25_PAD_D15__D15 0x088 0x280 0x000 0x00 0x000 #define MX25_PAD_D15__LD16 0x088 0x280 0x000 0x01 0x000 #define MX25_PAD_D15__GPIO_4_5 0x088 0x280 0x000 0x05 0x000 -#define MX25_PAD_D15__SDHC1_DAT7 0x088 0x280 0x4d8 0x06 0x000 +#define MX25_PAD_D15__ESDHC1_DAT7 0x088 0x280 0x4d8 0x06 0x000 #define MX25_PAD_D14__D14 0x08c 0x284 0x000 0x00 0x000 #define MX25_PAD_D14__LD17 0x08c 0x284 0x000 0x01 0x000 #define MX25_PAD_D14__GPIO_4_6 0x08c 0x284 0x000 0x05 0x000 -#define MX25_PAD_D14__SDHC1_DAT6 0x08c 0x284 0x4d4 0x06 0x000 +#define MX25_PAD_D14__ESDHC1_DAT6 0x08c 0x284 0x4d4 0x06 0x000 #define MX25_PAD_D13__D13 0x090 0x288 0x000 0x00 0x000 #define MX25_PAD_D13__LD18 0x090 0x288 0x000 0x01 0x000 #define MX25_PAD_D13__GPIO_4_7 0x090 0x288 0x000 0x05 0x000 -#define MX25_PAD_D13__SDHC1_DAT5 0x090 0x288 0x4d0 0x06 0x000 +#define MX25_PAD_D13__ESDHC1_DAT5 0x090 0x288 0x4d0 0x06 0x000 #define MX25_PAD_D12__D12 0x094 0x28c 0x000 0x00 0x000 #define MX25_PAD_D12__GPIO_4_8 0x094 0x28c 0x000 0x05 0x000 -#define MX25_PAD_D12__SDHC1_DAT4 0x094 0x28c 0x4cc 0x06 0x000 +#define MX25_PAD_D12__ESDHC1_DAT4 0x094 0x28c 0x4cc 0x06 0x000 #define MX25_PAD_D11__D11 0x098 0x290 0x000 0x00 0x000 #define MX25_PAD_D11__GPIO_4_9 0x098 0x290 0x000 0x05 0x000 @@ -236,12 +236,12 @@ #define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x00 0x000 #define MX25_PAD_LD8__UART4_RXD 0x0e8 0x2e0 0x570 0x02 0x000 #define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x05 0x000 -#define MX25_PAD_LD8__SDHC2_CMD 0x0e8 0x2e0 0x4e0 0x06 0x000 +#define MX25_PAD_LD8__ESDHC2_CMD 0x0e8 0x2e0 0x4e0 0x06 0x000 #define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x00 0x000 #define MX25_PAD_LD9__UART4_TXD 0x0ec 0x2e4 0x000 0x02 0x000 #define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x05 0x001 -#define MX25_PAD_LD9__SDHC2_CLK 0x0ec 0x2e4 0x4dc 0x06 0x000 +#define MX25_PAD_LD9__ESDHC2_CLK 0x0ec 0x2e4 0x4dc 0x06 0x000 #define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x00 0x000 #define MX25_PAD_LD10__UART4_RTS 0x0f0 0x2e8 0x56c 0x02 0x000 @@ -250,7 +250,7 @@ #define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x00 0x000 #define MX25_PAD_LD11__UART4_CTS 0x0f4 0x2ec 0x000 0x02 0x000 #define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x05 0x001 -#define MX25_PAD_LD11__SDHC2_DAT1 0x0f4 0x2ec 0x4e8 0x06 0x000 +#define MX25_PAD_LD11__ESDHC2_DAT1 0x0f4 0x2ec 0x4e8 0x06 0x000 #define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x00 0x000 #define MX25_PAD_LD12__CSPI2_MOSI 0x0f8 0x2f0 0x4a0 0x02 0x000 @@ -316,12 +316,12 @@ #define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x07 0x000 #define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x00 0x000 -#define MX25_PAD_CSI_D6__SDHC2_CMD 0x130 0x328 0x4e0 0x02 0x001 +#define MX25_PAD_CSI_D6__ESDHC2_CMD 0x130 0x328 0x4e0 0x02 0x001 #define MX25_PAD_CSI_D6__SIM1_PD0 0x130 0x328 0x000 0x04 0x000 #define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x05 0x000 #define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x00 0x000 -#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK 0x134 0x32C 0x4dc 0x02 0x001 +#define MX25_PAD_CSI_D7__ESDHC2_CLK 0x134 0x32C 0x4dc 0x02 0x001 #define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x05 0x000 #define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x00 0x000 @@ -336,22 +336,22 @@ #define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x00 0x000 #define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x01 0x000 -#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 0x140 0x338 0x4e4 0x02 0x001 +#define MX25_PAD_CSI_MCLK__ESDHC2_DAT0 0x140 0x338 0x4e4 0x02 0x001 #define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x05 0x000 #define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x00 0x000 #define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x01 0x000 -#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 0x144 0x33c 0x4e8 0x02 0x001 +#define MX25_PAD_CSI_VSYNC__ESDHC2_DAT1 0x144 0x33c 0x4e8 0x02 0x001 #define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x05 0x000 #define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x00 0x000 #define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x01 0x000 -#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 0x148 0x340 0x4ec 0x02 0x001 +#define MX25_PAD_CSI_HSYNC__ESDHC2_DAT2 0x148 0x340 0x4ec 0x02 0x001 #define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x05 0x000 #define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x00 0x000 #define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x01 0x000 -#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 0x14c 0x344 0x4f0 0x02 0x001 +#define MX25_PAD_CSI_PIXCLK__ESDHC2_DAT3 0x14c 0x344 0x4f0 0x02 0x001 #define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x05 0x000 #define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x00 0x000 @@ -419,37 +419,37 @@ #define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x05 0x000 /* - * Removing the SION bit from MX25_PAD_SD1_CMD__SD1_CMD breaks detecting an SD - * card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM - * Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon - * bug that configuring the SD1_CMD function doesn't enable the input path for - * this pin. + * Removing the SION bit from MX25_PAD_SD1_CMD__ESDHC1_CMD breaks detecting an + * SD card. According to the i.MX25 reference manual (e.g. Figure 23-2 in + * IMX25RM Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a + * silicon bug that configuring the ESDHC1_CMD function doesn't enable the input + * path for this pin. * This might have side effects for other hardware units that are connected to * that pin and use the respective function as input. */ -#define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000 +#define MX25_PAD_SD1_CMD__ESDHC1_CMD 0x190 0x388 0x000 0x10 0x000 #define MX25_PAD_SD1_CMD__CSPI2_MOSI 0x190 0x388 0x4a0 0x01 0x001 #define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x02 0x002 #define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x05 0x000 -#define MX25_PAD_SD1_CLK__SD1_CLK 0x194 0x38c 0x000 0x00 0x000 +#define MX25_PAD_SD1_CLK__ESDHC1_CLK 0x194 0x38c 0x000 0x00 0x000 #define MX25_PAD_SD1_CLK__CSPI2_MISO 0x194 0x38c 0x49c 0x01 0x001 #define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x02 0x002 #define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x05 0x000 -#define MX25_PAD_SD1_DATA0__SD1_DATA0 0x198 0x390 0x000 0x00 0x000 +#define MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x198 0x390 0x000 0x00 0x000 #define MX25_PAD_SD1_DATA0__CSPI2_SCLK 0x198 0x390 0x494 0x01 0x001 #define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x05 0x000 -#define MX25_PAD_SD1_DATA1__SD1_DATA1 0x19c 0x394 0x000 0x00 0x000 +#define MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x19c 0x394 0x000 0x00 0x000 #define MX25_PAD_SD1_DATA1__AUD7_RXD 0x19c 0x394 0x478 0x03 0x000 #define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x05 0x000 -#define MX25_PAD_SD1_DATA2__SD1_DATA2 0x1a0 0x398 0x000 0x00 0x000 +#define MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x1a0 0x398 0x000 0x00 0x000 #define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x02 0x002 #define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x05 0x000 -#define MX25_PAD_SD1_DATA3__SD1_DATA3 0x1a4 0x39c 0x000 0x00 0x000 +#define MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x1a4 0x39c 0x000 0x00 0x000 #define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x02 0x002 #define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x05 0x000 @@ -601,4 +601,28 @@ #define MX25_PAD_BOOT_MODE1__BOOT_MODE1 0x228 0x000 0x000 0x00 0x000 #define MX25_PAD_BOOT_MODE1__GPIO_4_31 0x228 0x000 0x000 0x05 0x000 +/* + * Compatibility defines for out-of-tree users. You should update if you make + * use of one of them. + */ +#define MX25_PAD_D15__SDHC1_DAT7 MX25_PAD_D15__ESDHC1_DAT7 +#define MX25_PAD_D14__SDHC1_DAT6 MX25_PAD_D14__ESDHC1_DAT6 +#define MX25_PAD_D13__SDHC1_DAT5 MX25_PAD_D13__ESDHC1_DAT5 +#define MX25_PAD_D12__SDHC1_DAT4 MX25_PAD_D12__ESDHC1_DAT4 +#define MX25_PAD_LD8__SDHC2_CMD MX25_PAD_LD8__ESDHC2_CMD +#define MX25_PAD_LD9__SDHC2_CLK MX25_PAD_LD9__ESDHC2_CLK +#define MX25_PAD_LD11__SDHC2_DAT1 MX25_PAD_LD11__ESDHC2_DAT1 +#define MX25_PAD_CSI_D6__SDHC2_CMD MX25_PAD_CSI_D6__ESDHC2_CMD +#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK MX25_PAD_CSI_D7__ESDHC2_CLK +#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 MX25_PAD_CSI_MCLK__ESDHC2_DAT0 +#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 MX25_PAD_CSI_VSYNC__ESDHC2_DAT1 +#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 MX25_PAD_CSI_HSYNC__ESDHC2_DAT2 +#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 MX25_PAD_CSI_PIXCLK__ESDHC2_DAT3 +#define MX25_PAD_SD1_CMD__SD1_CMD MX25_PAD_SD1_CMD__ESDHC1_CMD +#define MX25_PAD_SD1_CLK__SD1_CLK MX25_PAD_SD1_CLK__ESDHC1_CLK +#define MX25_PAD_SD1_DATA0__SD1_DATA0 MX25_PAD_SD1_DATA0__ESDHC1_DAT0 +#define MX25_PAD_SD1_DATA1__SD1_DATA1 MX25_PAD_SD1_DATA1__ESDHC1_DAT1 +#define MX25_PAD_SD1_DATA2__SD1_DATA2 MX25_PAD_SD1_DATA2__ESDHC1_DAT2 +#define MX25_PAD_SD1_DATA3__SD1_DATA3 MX25_PAD_SD1_DATA3__ESDHC1_DAT3 + #endif /* __DTS_IMX25_PINFUNC_H */ -- 2.14.1