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[209.132.180.67]) by mx.google.com with ESMTP id c14si12357748pgu.645.2018.02.01.00.02.23; Thu, 01 Feb 2018 00:02:38 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fSGVwYpm; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751635AbeBAIBw (ORCPT + 99 others); Thu, 1 Feb 2018 03:01:52 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:50678 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751272AbeBAIBs (ORCPT ); Thu, 1 Feb 2018 03:01:48 -0500 Received: by mail-wm0-f67.google.com with SMTP id f71so3952480wmf.0 for ; Thu, 01 Feb 2018 00:01:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:mime-version :in-reply-to:content-language:content-transfer-encoding; bh=eqQqnQRKNznFUeOk1fuglzhYMgY+aPiAdAmMkHcRLDE=; b=fSGVwYpmxcn8elcId4r6r+8rOi28lVLBjev0ZSrxZO+LFMv3FHGyjEB7QHgLtkeAxS r8sy7lghE4KGzEr485cskYgvJrVqgSrBKoIYyfa5xapW6uJ+jx+kK/8eexkIZji4Kauj cyUHsqooGY1iR8YBorJd4cjzZu5OPXYRDX3Vc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=eqQqnQRKNznFUeOk1fuglzhYMgY+aPiAdAmMkHcRLDE=; b=k/tN0DXJhJYCAXITi2/v1wvJ3OLh2p7GE3yrYy1MGO5ZSGF1SZbfETh5PR5Wt+6Zu6 oAyI8zpoYKqEqyI1nTwd+iFyRnxdjklMzuTELJ0Ns4J5si/R0q6GzSYhQ5N6t7yGQjxr X5oOmdyxM5IzWRR0qoT9wZO2b0YH52WOlN3hAIn1VqmYPyB0OYFiurWilUbEWwLchsJ5 JO67YWqwhcNKyLxzS0aJXo/awgt3ZO2nCrMV14OcD93yMV082J/SFo5kjWxKF1QzOSxE KXsiizVg3YZYcJaYBlSFKyEhXDBFVRS2N+SkcAvjQc99+N9WqCW/dYGu8tm9fE22yS91 83bg== X-Gm-Message-State: AKwxyteWSLhtqS8ET8k2J1exVMm42i/VqKzrZXOdW3Zi/d2HV3ZhNC+g ZWc2yrRpKAg7BZmQdvS7CDDNjw== X-Received: by 10.28.241.14 with SMTP id p14mr25189072wmh.20.1517472107240; Thu, 01 Feb 2018 00:01:47 -0800 (PST) Received: from [10.44.66.8] ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id h200sm1665446wme.11.2018.02.01.00.01.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Feb 2018 00:01:46 -0800 (PST) Subject: Re: [PATCH v11 2/6] mailbox: qcom: Create APCS child device for clock controller To: Jassi Brar Cc: Bjorn Andersson , Stephen Boyd , Michael Turquette , Rob Herring , linux-clk@vger.kernel.org, Linux Kernel Mailing List , linux-arm-msm@vger.kernel.org, Devicetree List References: <20171205154701.27730-1-georgi.djakov@linaro.org> <20171205154701.27730-3-georgi.djakov@linaro.org> <20171224050625.GH12655@minitux> <549f02e5-19d7-8cec-674f-247dfb2d2467@linaro.org> From: Georgi Djakov Message-ID: <384da443-a206-8db3-0a5f-90a68b7f42c2@linaro.org> Date: Thu, 1 Feb 2018 10:01:44 +0200 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 02/01/2018 08:57 AM, Jassi Brar wrote: > On Thu, Feb 1, 2018 at 12:10 AM, Georgi Djakov wrote: >> >> Hi Jassi, >> >> On 01/27/2018 05:44 AM, Jassi Brar wrote: >>> On Thu, Jan 4, 2018 at 10:26 PM, Georgi Djakov wrote: >>>> Hi Jassi, >>>> >>>> On 12/29/2017 08:14 AM, Jassi Brar wrote: >>>>> Hi Bjorn, >>>>> >>>>> On Sun, Dec 24, 2017 at 10:36 AM, Bjorn Andersson >>>>> wrote: >>>>>> On Fri 22 Dec 20:57 PST 2017, Jassi Brar wrote: >>>>>> >>>>>>> On Tue, Dec 5, 2017 at 9:16 PM, Georgi Djakov wrote: >>>>>>>> There is a clock controller functionality provided by the APCS hardware >>>>>>>> block of msm8916 devices. The device-tree would represent an APCS node >>>>>>>> with both mailbox and clock provider properties. >>>>>>>> >>>>>>> The spec might depict a 'clock' box and 'mailbox' box inside the >>>>>>> bigger APCS box. However, from the code I see in this patchset, they >>>>>>> are orthogonal and can & should be represented as independent DT >>>>>>> nodes. >>>>>> >>>>>> The APCS consists of a number of different hardware blocks, one of them >>>>>> being the "APCS global" block, which is what this node and drivers >>>>>> relate to. On 8916 this contains both the IPC register and clock >>>>>> control. But it's still just one block according to the hardware >>>>>> specification. >>>>>> >>>>>> As such DT should describe the one hardware block by one node IMHO. >>>>>> >>>>> In my even humbler opinion, DT should describe a h/w functional unit >>>>> which _could_ be seen as a standalone component. >>>> >>>> The APCS is one separate register block related to the CPU cluster. I >>>> haven't seen any strict guidelines for such cases in the DT docs, and >>>> during the discussion got the impression that this is the preferred >>>> binding. Rob has also reviewed the binding, so we should be fine to move >>>> forward with this one. >>>> >>> Well, I can't overrule Rob. But I am really not happy with random >>> device spawning from mailbox drivers. I know there are such instances >>> already in the kernel but that doesn't make it legit... unless there >>> is some hard dependency. Is there? >> >> The dependency is that on this SoC, these functionalities are combined >> into this "CPU subsystem" block. >> > I see the register space is shared between mailbox and the clock. So I > guess, yes, simply creating a device here and passing the common > regmap is tidier. Which patches are already picked up? Patches 3, 4 and 6 are already picked into the clk tree. Still pending are patches 1, 2 and 5. Thanks, Georgi