Received: by 10.223.176.5 with SMTP id f5csp2674745wra; Thu, 1 Feb 2018 04:23:03 -0800 (PST) X-Google-Smtp-Source: AH8x226LtLNvIQVY7K1HMPGM5i1CWEHpW7QID61ouk0T6pUUIl4Z/iv+1HurMKAPgbXjC0dqPJNz X-Received: by 10.98.196.75 with SMTP id y72mr37034346pff.73.1517487783856; Thu, 01 Feb 2018 04:23:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517487783; cv=none; d=google.com; s=arc-20160816; b=xdSHGB8RFSsBF2HcNOgZ8gux68TkQYDcLDtFNf+ed52ALAorAg/xdvVZX3F3hTaDxI HLA2BABStcQ0fxp89NZx9zj6wYSlQoldLUIhqHCLUTbIbSqUykj09b98XrFspNi2OXj6 4HLmqy8QAAw3VDL5Yq1GeoIAfnjOmpj8ucob5lHHrqFuW5XCYF9HWigUrRl58+ji9Tkm 8VODWljIQW93UDZOqvVbSNAsI0loRPGzaMZ9G6kpMxDAFzN4Ma6J3kLPtFAfmEciTDPm ckcS6YxK0czQkbyRLynjPCfnX8R5bgvSUWbj5a1AQSS8KYixfnP5UOLuJ/8+GhtFSNRC ra1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-language :content-transfer-encoding:in-reply-to:mime-version:user-agent:date :message-id:from:references:cc:to:subject:arc-authentication-results; bh=3RqRpHlP0wMVr7LJYzXO7OTjmUDflU+fZb4XV1H4Zyg=; b=YWqS7ghkU/6fDcWfp3VahTDQNBOaoQWfZl4KraQtQZfxiLT1coQmlH+C38V4hVkocL aA/UFbiirK/Di0B+XV7rtSewXMqRZDWMEmpPsk6x4XLIc3TV8RHEUOuMvasTOwNmRHIC K4nkWoryUto8s8XkNKRhOvPg3q556QqGSWeLrRpXIYfKHoDhVLQOC3+qkM6YIU0Zma6A v7BmlBl/qT9CslMEiaF092aXze+9SlOl2CfpLrntc7iwmmKYSaeSMOcInuIbLIyd9XVB C1x6f/bg4S8cgJn6uMv7JG/FLABIt3UnOxyP6zb7NNx7CsgsbeKY+cqqZHNAXDuVkqkI /7dg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c21-v6si4052893plo.46.2018.02.01.04.22.49; Thu, 01 Feb 2018 04:23:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752459AbeBAMWL (ORCPT + 99 others); Thu, 1 Feb 2018 07:22:11 -0500 Received: from smtp.eu.citrix.com ([185.25.65.24]:47763 "EHLO SMTP.EU.CITRIX.COM" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752098AbeBAMWI (ORCPT ); Thu, 1 Feb 2018 07:22:08 -0500 X-IronPort-AV: E=Sophos;i="5.46,444,1511827200"; d="scan'208";a="67059955" Subject: Re: [PATCH] x86/xen: init %gs very early to avoid page faults with stack protector To: Juergen Gross , , CC: , References: <20180201121601.1268-1-jgross@suse.com> From: Andrew Cooper Message-ID: <66ad81d7-0230-d0a5-f4fb-9dbbd8162884@citrix.com> Date: Thu, 1 Feb 2018 12:22:05 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.2 MIME-Version: 1.0 In-Reply-To: <20180201121601.1268-1-jgross@suse.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Content-Language: en-GB X-ClientProxiedBy: AMSPEX02CAS02.citrite.net (10.69.22.113) To AMSPEX02CL02.citrite.net (10.69.22.126) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 01/02/18 12:16, Juergen Gross wrote: > When running as Xen pv guest %gs is initialized some time after > C code is started. Depending on stack protector usage this might be > too late, resulting in page faults. > > So setup %gs and MSR_GS_BASE in assembly code already. > > Cc: stable@vger.kernel.org > Signed-off-by: Juergen Gross > --- > arch/x86/xen/xen-head.S | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/arch/x86/xen/xen-head.S b/arch/x86/xen/xen-head.S > index 497cc55a0c16..b47d87076efb 100644 > --- a/arch/x86/xen/xen-head.S > +++ b/arch/x86/xen/xen-head.S > @@ -9,7 +9,9 @@ > > #include > #include > +#include > #include > +#include > #include > > #include > @@ -35,6 +37,18 @@ ENTRY(startup_xen) > mov %_ASM_SI, xen_start_info > mov $init_thread_union+THREAD_SIZE, %_ASM_SP > > + /* Set up %gs. > + * > + * The base of %gs always points to the bottom of the irqstack > + * union. If the stack protector canary is enabled, it is > + * located at %gs:40. Note that, on SMP, the boot cpu uses > + * init data section till per cpu areas are set up. > + */ > + movl $MSR_GS_BASE,%ecx > + movq $INIT_PER_CPU_VAR(irq_stack_union),%rax > + cdq > + wrmsr You surely want a #ifdef __x86_64__ ?  This path is common to the 32bit entry as well? ~Andrew > + > jmp xen_start_kernel > END(startup_xen) > __FINIT