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[209.132.180.67]) by mx.google.com with ESMTP id o11si1092740pgn.796.2018.02.01.04.24.34; Thu, 01 Feb 2018 04:24:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=OExoQeqV; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752408AbeBAMYI (ORCPT + 99 others); Thu, 1 Feb 2018 07:24:08 -0500 Received: from fllnx210.ext.ti.com ([198.47.19.17]:24292 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752126AbeBAMYH (ORCPT ); Thu, 1 Feb 2018 07:24:07 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id w11CN2f7027307; Thu, 1 Feb 2018 06:23:02 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517487782; bh=fYpygnQ+J7xg8y/qj5OZZx87TI1W7GE/T2NiQpvbo4E=; h=Subject:From:To:CC:References:Date:In-Reply-To; b=OExoQeqVOZ0h8yCcEvEaSilJ14rJDBBB8XDZN29miq5F93GWZhLzEEF07ulVmnQCB O+Og8EID6rpK7m7v/pojOsCfLqkIfgKMS25JBz+BNVh8hM9hWGFvjpLPcTUH033YMR nNxPjQpgh37uU84AlLhHe4gLu9qhkXAegwTe6gZc= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w11CN2co030413; Thu, 1 Feb 2018 06:23:02 -0600 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Thu, 1 Feb 2018 06:23:02 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Thu, 1 Feb 2018 06:23:02 -0600 Received: from [172.24.190.171] (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w11CMv2g016170; Thu, 1 Feb 2018 06:22:58 -0600 Subject: Re: [PATCH v6 02/41] clk: davinci: New driver for davinci PLL clocks From: Sekhar Nori To: David Lechner , , , CC: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Kevin Hilman , Bartosz Golaszewski , Adam Ford , References: <1516468460-4908-1-git-send-email-david@lechnology.com> <1516468460-4908-3-git-send-email-david@lechnology.com> Message-ID: <2a833d5c-4cd7-5c55-4b4a-a02bd7fde6d9@ti.com> Date: Thu, 1 Feb 2018 17:52:57 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thursday 01 February 2018 01:31 PM, Sekhar Nori wrote: > One thing missing is DIV4.5 clock. It will be nice to add that too, > mostly just because it will make the binding complete. Ah, ignore this comment please. I noticed that its part of cfgchip clocks (which makes sense). Thanks, Sekhar