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[209.132.180.67]) by mx.google.com with ESMTP id u27si1654000pfk.385.2018.02.01.04.27.12; Thu, 01 Feb 2018 04:27:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P70oHK+e; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752471AbeBAM0F (ORCPT + 99 others); Thu, 1 Feb 2018 07:26:05 -0500 Received: from mail-oi0-f66.google.com ([209.85.218.66]:39309 "EHLO mail-oi0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752249AbeBAM0C (ORCPT ); Thu, 1 Feb 2018 07:26:02 -0500 Received: by mail-oi0-f66.google.com with SMTP id j188so11802642oib.6 for ; Thu, 01 Feb 2018 04:26:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=hBGh/JbxL2F1FUl3L+Kx4ga4ur1zfzJzMAytbsOTJ5o=; b=P70oHK+eDW/M4DzDpCNJx80z/loThKvtcuFJJYCoNmLZZpgv6Ij5CajoLZDwcKJgkH yC/8Ca8KF3uAFjoBIVKY31Ju4ps1gjQuAhQhUSj0AePHBqWsq536O6/jSvVNRWNKdg2I 1tKY8TU0AdOHesR1tMjKybwQGmX8kWOA9Cu7E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=hBGh/JbxL2F1FUl3L+Kx4ga4ur1zfzJzMAytbsOTJ5o=; b=gBXb/Cq81HaoFe7Vth/P6YIbponxe5YSP4E0gIThRjqar89lLVuDGuFmMveaqAhaHj DINQ7BE9yn5AhHWRfUIMlVlYvNT6V1Bldy5gntj+2aBypQblzc5q5QANYDqZ8TTYG3u3 K2Tt7Iwmue6FGC7rc7+oc6ENyQgrgB5LTfvx0Q5ty/rPMNRlxJKtxKkCb7VSX9XtAPdM ZyaYHLLRRkiQw7FzV/oj138I9DX9vqTWFIRIyfmcDSz+3OYgzQrNPvU0hbLnvLUxStlH i61D9nRAHzi+ZfOaPKNciGHVOS1gS+jLNmGql5OlnEmU0ab4/qBiuQsTpWIT8OLSaiEq hFmA== X-Gm-Message-State: AKwxytfoHk/RkojH/ij6yb5GFknM/scGnUQI6v/75fKTZZLZ7N10pgUL PjRZ8dP5ao+Ea0NfkdAyBT7Gpu2NL2HmYEy7vzmckg== X-Received: by 10.202.80.200 with SMTP id e191mr3938257oib.333.1517487961569; Thu, 01 Feb 2018 04:26:01 -0800 (PST) MIME-Version: 1.0 Received: by 10.157.28.174 with HTTP; Thu, 1 Feb 2018 04:26:01 -0800 (PST) In-Reply-To: <20180201121753.GB690@gmail.com> References: <2834309f69a1ec37b84a33f153a3d0b90336bcc6.1517313987.git.baolin.wang@linaro.org> <20180201121753.GB690@gmail.com> From: Baolin Wang Date: Thu, 1 Feb 2018 20:26:01 +0800 Message-ID: Subject: Re: [PATCH 2/2] gpio: Add GPIO driver for Spreadtrum SC9860 platform To: Marcus Folkesson Cc: Linus Walleij , Rob Herring , Mark Rutland , DTML , LKML , "open list:GPIO SUBSYSTEM" , Mark Brown Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Markus, On 1 February 2018 at 20:17, Marcus Folkesson wrote: > Hi Baolin, > > On Tue, Jan 30, 2018 at 08:07:43PM +0800, Baolin Wang wrote: >> The Spreadtrum SC9860 platform GPIO controller contains 16 groups and >> each group contains 16 GPIOs. Each GPIO can set input/output and has >> the interrupt capability. >> >> Signed-off-by: Baolin Wang >> --- >> diff --git a/drivers/gpio/gpio-sprd.c b/drivers/gpio/gpio-sprd.c >> new file mode 100644 >> index 0000000..af59b9f >> --- /dev/null >> +++ b/drivers/gpio/gpio-sprd.c >> @@ -0,0 +1,301 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Copyright (C) 2018 Spreadtrum Communications Inc. >> + * Copyright (c) 2018 Linaro Ltd. >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +/* GPIO registers definition */ >> +#define SPRD_GPIO_DATA 0x0 >> +#define SPRD_GPIO_DMSK 0x4 >> +#define SPRD_GPIO_DIR 0x8 >> +#define SPRD_GPIO_IS 0xc >> +#define SPRD_GPIO_IBE 0x10 >> +#define SPRD_GPIO_IEV 0x14 >> +#define SPRD_GPIO_IE 0x18 >> +#define SPRD_GPIO_RIS 0x1c >> +#define SPRD_GPIO_MIS 0x20 >> +#define SPRD_GPIO_IC 0x24 >> +#define SPRD_GPIO_INEN 0x28 >> + >> +/* We have 16 groups GPIOs and each group contain 16 GPIOs */ >> +#define SPRD_GPIO_GROUP_NR 16 >> +#define SPRD_GPIO_NR 256 >> +#define SPRD_GPIO_GROUP_SIZE 0x80 >> +#define SPRD_GPIO_GROUP_MASK GENMASK(15, 0) >> +#define SPRD_GPIO_BIT(x) ((x) & (SPRD_GPIO_GROUP_NR - 1)) >> + >> +struct sprd_gpio { >> + struct gpio_chip chip; >> + void __iomem *base; >> + spinlock_t lock; >> + int irq; >> +}; >> + >> +static inline void __iomem *sprd_gpio_group_base(struct sprd_gpio *sprd_gpio, >> + unsigned int group) >> +{ >> + return sprd_gpio->base + SPRD_GPIO_GROUP_SIZE * group; >> +} >> + >> +static void sprd_gpio_update(struct gpio_chip *chip, unsigned int offset, >> + unsigned int reg, unsigned int val) >> +{ >> + struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip); >> + void __iomem *base = sprd_gpio_group_base(sprd_gpio, >> + offset / SPRD_GPIO_GROUP_NR); >> + u32 shift = SPRD_GPIO_BIT(offset); >> + unsigned long flags; >> + u32 orig, tmp; >> + >> + spin_lock_irqsave(&sprd_gpio->lock, flags); >> + orig = readl_relaxed(base + reg); >> + >> + tmp = (orig & ~BIT(shift)) | (val << shift); >> + writel_relaxed(tmp, base + reg); >> + spin_unlock_irqrestore(&sprd_gpio->lock, flags); >> +} >> + >> +static int sprd_gpio_read(struct gpio_chip *chip, unsigned int offset, >> + unsigned int reg) >> +{ >> + struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip); >> + void __iomem *base = sprd_gpio_group_base(sprd_gpio, >> + offset / SPRD_GPIO_GROUP_NR); >> + u32 value = readl_relaxed(base + reg) & SPRD_GPIO_GROUP_MASK; >> + u32 shift = SPRD_GPIO_BIT(offset); >> + >> + return !!(value & BIT(shift)); >> +} >> + >> +static int sprd_gpio_request(struct gpio_chip *chip, unsigned int offset) >> +{ >> + sprd_gpio_update(chip, offset, SPRD_GPIO_DMSK, 1); >> + return 0; >> +} > > Better to change the function to void since the return value is not > valueable. The function prototype of gpio_chip structure need one return value, so we need give one returned value though it is no meaningless. > >> + >> +static void sprd_gpio_free(struct gpio_chip *chip, unsigned int offset) >> +{ >> + sprd_gpio_update(chip, offset, SPRD_GPIO_DMSK, 0); >> +} >> + >> +static int sprd_gpio_direction_input(struct gpio_chip *chip, >> + unsigned int offset) >> +{ >> + sprd_gpio_update(chip, offset, SPRD_GPIO_DIR, 0); >> + sprd_gpio_update(chip, offset, SPRD_GPIO_INEN, 1); >> + return 0; >> +} > > Same here > > >> + >> +static int sprd_gpio_direction_output(struct gpio_chip *chip, >> + unsigned int offset, int value) >> +{ >> + sprd_gpio_update(chip, offset, SPRD_GPIO_DIR, 1); >> + sprd_gpio_update(chip, offset, SPRD_GPIO_INEN, 0); >> + sprd_gpio_update(chip, offset, SPRD_GPIO_DATA, value); >> + return 0; >> +} > > and here. > > > Thanks, > Marcus Folkesson > > > -- Baolin.wang Best Regards