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[209.132.180.67]) by mx.google.com with ESMTP id r2-v6si2144001pli.324.2018.02.01.07.36.34; Thu, 01 Feb 2018 07:36:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=BtkaspWP; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751942AbeBAPgI (ORCPT + 99 others); Thu, 1 Feb 2018 10:36:08 -0500 Received: from mail-oi0-f66.google.com ([209.85.218.66]:43638 "EHLO mail-oi0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751472AbeBAPgF (ORCPT ); Thu, 1 Feb 2018 10:36:05 -0500 Received: by mail-oi0-f66.google.com with SMTP id 4so13640273ois.10; Thu, 01 Feb 2018 07:36:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=7NrDr9SEyHkhzdZwcF67R1ycLo+fnqOfR8hkrM8czS0=; b=BtkaspWP30kPDo5IPQYPALpP8Fa7ch2yQgt6sTIrjqEseCti4Dwfzu1w51oOvjdfgV LF4/RmWOnXtcl9FA/iSoxwl5tGLElhjffFi/TDGsmfqnbROP2bTM7YNQfSzXNs0d6z6o K/gOWseczOqDakPrOWCdJzUpJSnx6uXPsMBy0668p+FfxxNVfT2+/ThJqdGzR5V4rCwc yih+TECF+kz5SSR9dhKzFcUfAgw1xA0YFRJMfVsEVx41AExULmGSm7nJ4kr9D76k/EYv 949VEw/UR+uNsZwNGUND2yVcmBsnhDfkEduf2d3mA8+vgqCHCRkyObqLD/2E9VXevJfU slkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:sender:in-reply-to:references:from :date:message-id:subject:to:cc; bh=7NrDr9SEyHkhzdZwcF67R1ycLo+fnqOfR8hkrM8czS0=; b=PIb93MfaENPwphVMiuNgc4g9KU0ZyZ7f8I1gpqcAsdHVLpWQM/5BF0vJuX3I9HU2dC TcroUad8ez6BMPSD1L1Qd4+QcIJTlBFd3ce5KsWvLQ/FEEzy1xrSLpvB5OzYK+k5uAqI rbDHWyMfBh1IJvigAtzlrgjjB50tBmpP7IJWucWSeg4yPwnw6h+x1BgOPpTITgJrkMDG GiJLWr/ct/wvnZMNYziE3CuRTg8XhSMzZHW6aQvJxmp80rrXbo3M98kmZclsr7PKEetU LJe1JWFqsyo9xKhRoTRvSoUhb9Vpb+IIrKVEEWxi8WxZzwIVhzIhlVDr+iORwG+uWz6N m/fg== X-Gm-Message-State: AKwxytejtKIKUmkMGhcMSRLJULEnduQ6G3aaFFVZ8KbTfYqumpNKbuO1 PpX6tAWEBEh+Agr8UtPdDO0nHsg/ir8XMKgUplA= X-Received: by 10.202.91.69 with SMTP id p66mr17111552oib.64.1517499365061; Thu, 01 Feb 2018 07:36:05 -0800 (PST) MIME-Version: 1.0 Received: by 10.157.68.33 with HTTP; Thu, 1 Feb 2018 07:36:04 -0800 (PST) In-Reply-To: <20180201152908.mdei742x5k4fye6p@flea.lan> References: <20180129082533.6edmqgbauo6q5dgz@flea.lan> <20180130075441.rqxzkwero6sdfak6@flea.lan> <20180130095916.GA23047@ulmo> <20180130100150.GB23047@ulmo> <20180131072910.ajp3jc5dmetsjtf2@flea.lan> <20180201152908.mdei742x5k4fye6p@flea.lan> From: Arnd Bergmann Date: Thu, 1 Feb 2018 16:36:04 +0100 X-Google-Sender-Auth: IfSsIKaFGmizUXlozlVdnfCkBKY Message-ID: Subject: Re: [PATCH v6 2/2] media: V3s: Add support for Allwinner CSI. To: Maxime Ripard Cc: Thierry Reding , Dave Martin , Linus Walleij , Yong Deng , Mauro Carvalho Chehab , Rob Herring , Mark Rutland , Chen-Yu Tsai , "David S. Miller" , Greg Kroah-Hartman , Hans Verkuil , Randy Dunlap , Stanimir Varbanov , Hugues Fruchet , Yannick Fertre , Philipp Zabel , Benjamin Gaignard , Ramesh Shanmugasundaram , Sakari Ailus , Rick Chang , Linux Media Mailing List , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux ARM , "linux-kernel@vger.kernel.org" , linux-sunxi , megous@megous.com, Thomas Petazzoni Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Feb 1, 2018 at 4:29 PM, Maxime Ripard wrote: > On Wed, Jan 31, 2018 at 10:37:37AM +0100, Arnd Bergmann wrote: >> On Wed, Jan 31, 2018 at 8:29 AM, Maxime Ripard > >> I can think of a couple of other problems that may or may not be >> relevant in the future that would require a more complex solution: >> >> - a device that is a bus master on more than one bus, e.g. a >> DMA engine that can copy between the CPU address space and >> another memory controller that is not visible to the CPU >> >> - a device that is connected to main memory both through an IOMMU >> and directly through its parent bus, and the device itself is in >> control over which of the two it uses (usually the IOMMU would >> contol whether a device is bypassing translation) >> >> - a device that has a single DMA address space with some form >> of non-linear mapping to one or more parent buses. Some of these >> can be expressed using the parent's dma-ranges properties, but >> our code currently only looks at the first entry in dma-ranges. > > As far as I know, we're in neither of these cases. The point here was more about the general question of where we are heading with the complexity of finding the right DMA settings. It's already too complicated for anyone to fully understand what is going on with DMA masks, offset, coherency etc when we look at the existing DT bindings. Adding more complexity makes it worse, so if anyone else is in need of a solution for the issues above, we should try to accommodate their needs at the same time to avoid adding more complexity now and again later on if we can come up with a way that works for everyone now. Arnd