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[209.132.180.67]) by mx.google.com with ESMTP id j8si118757pgp.160.2018.02.01.08.51.13; Thu, 01 Feb 2018 08:51:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=UgSWL5H4; dkim=pass header.i=@codeaurora.org header.s=default header.b=KcG9vqjj; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752724AbeBAQuF (ORCPT + 99 others); Thu, 1 Feb 2018 11:50:05 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:36898 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752680AbeBAQt5 (ORCPT ); Thu, 1 Feb 2018 11:49:57 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 435F061160; Thu, 1 Feb 2018 16:49:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1517503797; bh=BfWOQgATDiVvCISl3CA5xqb67EBOCJi/0NzsGZkQJqc=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=UgSWL5H4uu/7LlBfP5CXa5pjgbZd5t32FzNy1GJ+0orBmcwBXwLRG6aAbK3C6Eg1p 40uIfc/YixYM7v9za84JacWgPR/WpVcJjHJJAnezmSFtc5vMex9nJJ6kF36DDYBILF wbjbQFqUYtbP8pwdg+Y+lr1rWde3bZNEx1DyBpuU= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from localhost (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id B4D0D60112; Thu, 1 Feb 2018 16:49:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1517503796; bh=BfWOQgATDiVvCISl3CA5xqb67EBOCJi/0NzsGZkQJqc=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=KcG9vqjj0YuKyXukTPV0FZhqAwOGR4mB7CQBBUlpUyneGwytlrAqWOowYVEmm7V5s pRWikuPDAcapKCNyYxBKRbQkz9geBcRtaH+a/YFT/x5t+HGlzPMhDeuMPsdzlSxcf9 XddTq03U7mDZA+XOs/sgMte0LewvAX32ganU/MwQ= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B4D0D60112 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org Date: Thu, 1 Feb 2018 16:49:56 +0000 From: Lina Iyer To: Marc Zyngier Cc: tglx@linutronix.de, jason@lakedaemon.net, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, sboyd@codeaurora.org, rnayak@codeaurora.org, asathyak@codeaurora.org Subject: Re: [PATCH RFC 1/4] drivers: irqchip: pdc: add support for PDC interrupt controller Message-ID: <20180201164956.GB13231@codeaurora.org> References: <20180123175656.11942-1-ilina@codeaurora.org> <20180123175656.11942-2-ilina@codeaurora.org> <9dd8307c-4906-4707-d4d7-2ef0fc8307b6@arm.com> <20180130175654.GC20815@codeaurora.org> <619608bb-a9c5-27a1-2383-5f6b2f455499@arm.com> <20180131162432.GA13231@codeaurora.org> <83cfda67-511f-aa83-8eff-214c08de25e4@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: <83cfda67-511f-aa83-8eff-214c08de25e4@arm.com> User-Agent: Mutt/1.9.2 (2017-12-15) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jan 31 2018 at 16:46 +0000, Marc Zyngier wrote: >On 31/01/18 16:24, Lina Iyer wrote: >> On Tue, Jan 30 2018 at 18:11 +0000, Marc Zyngier wrote: >>> On 30/01/18 17:56, Lina Iyer wrote: >>>> On Wed, Jan 24 2018 at 14:20 +0000, Marc Zyngier wrote: >>>>> On 23/01/18 17:56, Lina Iyer wrote: >>>>>> From : Archana Sathyakumar >>>>>> >>>>>> The Power Domain Controller (PDC) hardware block on Qualcomm SoCs houses >>>>>> an interrupt controller along with other domain control functions to >>>>>> handle interrupt related functions like handle falling edge or active >>>>>> low which are not detected at the GIC and handle wakeup interrupts. >>>>>> >>>>>> The interrupt controller is on an always-on domain for the purpose of >>>>>> waking up the processor, but only a subset of the processor's interrupts >>>>>> are routed through the PDC to the GIC. The PDC powers on the processor's >>>>>> domain, bringing the domain out of low power mode and replays the >>>>>> pending interrupts so the GIC may wake up the processor. >>>>>> >>>>>> Signed-off-by: Archana Sathyakumar >>>>>> Signed-off-by: Lina Iyer >>>>>> [Lina: Split out DT bindings target data and initialization changes] >>>>>> --- >>>> >> We looked at tegra's implementation and it appears similar, thought they >> don't seemt to have the same complexity. > >Exactly. They are pretty similar. Hence my suggestion to adopt the same >approach, which you don't seem to agree with. > I am reworking the driver based on what you have suggested in this thread. Will submit a patchset for review in the next couple of days. Once again, thank you for your time Marc. -- Lina