From: "Kathy Frazier" <kfrazier@mdc-dayton.com>
To: <linux-kernel@vger.kernel.org>, <herbert@13thfloor.at>
Subject: RE: Problems related to DMA or DDR memory on Intel 845 chipset?
Date: Mon, 28 Jul 2003 16:31:13 -0500
Message-ID: <PMEMILJKPKGMMELCJCIGCEIOCDAA.kfrazier@mdc-dayton.com>
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Herbert,

>to cut this short, you are initiating a dma transfer from
>within the kernel, and after it is finished, an itnerrupt
>should occur? AFAIK, this interrupt is generated by the
>dma logic (controller) so I'm a little confused ...

Sorry for the confusion!  My driver sets up our device for a DMA (address
and length) and then gives the command
for the DMA to start.  Once the device has completed the transfer, it
asserts its interrupt, the driver clears it and proceeds to set up the next
data transfer.  It runs for awhile, but then eventually hangs (I don't get
interrupts and neither does anything else - keyboard, ethernet, etc).  I
simply added debug to do_IRQ in the kernel to track the desired IRQ.  I also
added a routine to read the 8259 Interrupt Controller Registers when
requested.  Then I had a user app and driver which simply called this new
new routine in the kernel to return the status of the 8259 and the debug
counters I added to do_IRQ.  Once the system failed, this debug information
showed that not only was Linux NOT receiving the interrupt, but neither was
the 8259.  When I changed my driver to poll the device for DMA completion
instead of rely on an interrupt, it still locked up.

>memtest is usually suggested, when it is not sure that
>the hardware is working correctly, especially the memory.

I tried it for kicks.  It ran for a couple of hours and produced NO errors.

. . . Meanwhile, I made another discovery on the internet that indicates
that DMA is not supported with an ICH4 controller (which is what this system
has) until Linux version 2.5.12 (we're using 2.4.20-8).  See:
http://64.143.3.64/downloads/drivers/845/perform/linux/udma.htm.  I posted a
question concerning this to linux-kernel.  See thread:  DMA not supported
with Intel ICH4 I/O controller?  Unfortunately, I have not received any
response that supports or refutes this.  Any thoughts?

Thanks,
Kathy


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