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[209.132.180.67]) by mx.google.com with ESMTP id bc1-v6si1590185plb.250.2018.02.02.02.58.17; Fri, 02 Feb 2018 02:58:32 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=temperror (no key for signature) header.i=@micronovasrl.com header.s=dkim header.b=KyXzy3fC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751582AbeBBK53 (ORCPT + 99 others); Fri, 2 Feb 2018 05:57:29 -0500 Received: from mail.micronovasrl.com ([212.103.203.10]:42466 "EHLO mail.micronovasrl.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751129AbeBBK5W (ORCPT ); Fri, 2 Feb 2018 05:57:22 -0500 Received: from mail.micronovasrl.com (mail.micronovasrl.com [127.0.0.1]) by mail.micronovasrl.com (Postfix) with ESMTP id 02249B00D47 for ; Fri, 2 Feb 2018 11:57:20 +0100 (CET) Authentication-Results: mail.micronovasrl.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=micronovasrl.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=micronovasrl.com; h=content-transfer-encoding:content-language:content-type :content-type:in-reply-to:mime-version:user-agent:date:date :message-id:from:from:references:to:subject:subject; s=dkim; t= 1517569040; x=1518433041; bh=srZgulXkWpbhoqOeNPJV9AxX8crKamaz6Ay sn3Ellr8=; b=KyXzy3fCUTJ4GxGXedcLim0IL/R/UELJ4HYRAl6rcwJHDas1D9U ajhlBeg7XmwHXkgvw/NC0J2/dmlMFEwuS0LMctiy9PGdLUOnqGntGf06FVSvIegA 5SyYiJElS+7SfaBGTnK7KL8DFYsFB8Zmlen1ginX/U3ojlWdxpSwYhgo= X-Virus-Scanned: Debian amavisd-new at mail.micronovasrl.com X-Spam-Flag: NO X-Spam-Score: -2.9 X-Spam-Level: X-Spam-Status: No, score=-2.9 tagged_above=-10 required=4.5 tests=[ALL_TRUSTED=-1, BAYES_00=-1.9] autolearn=ham autolearn_force=no Received: from mail.micronovasrl.com ([127.0.0.1]) by mail.micronovasrl.com (mail.micronovasrl.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id 8IVqdBJghUWn for ; Fri, 2 Feb 2018 11:57:20 +0100 (CET) Received: from [192.168.2.69] (62-11-51-166.dialup.tiscali.it [62.11.51.166]) by mail.micronovasrl.com (Postfix) with ESMTPSA id 975AAB00688; Fri, 2 Feb 2018 11:57:19 +0100 (CET) Subject: Re: [PATCH] clk: sunxi-ng: ccu-sun4i-a10: Fix mali changing dclk frequency To: Maxime Ripard Cc: Chen-Yu Tsai , Michael Turquette , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org References: <1517354639-92978-1-git-send-email-giulio.benetti@micronovasrl.com> <20180131084349.du2ijvhh5rxa5vvt@flea.lan> <7be1e297-4fac-a7a2-a8cc-54061d4e2fde@micronovasrl.com> <20180201124551.kfyz6frx4lcx4wbz@flea.lan> <8c2fef37-8eb6-38c6-de3d-547edafac8b7@micronovasrl.com> <20180202105304.gow2znzgxqmuxgol@flea.lan> From: Giulio Benetti Message-ID: <1b3d96ae-c6e6-4f58-b140-7b1738c12adc@micronovasrl.com> Date: Fri, 2 Feb 2018 11:57:20 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <20180202105304.gow2znzgxqmuxgol@flea.lan> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Language: it Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Il 02/02/2018 11:53, Maxime Ripard ha scritto: > Hi, > > On Thu, Feb 01, 2018 at 05:17:11PM +0100, Giulio Benetti wrote: >>>>> What kernel version did you use? >>>> >>>> Latest mainline. >>> >>> I guess this patch could fix it: >>> http://code.bulix.org/1kitrq-268936?raw >> >> This should prevent from modifying parent clock. But my problem was >> different. >> >> On A20, gpu_clk can have different PLL, not I've found out the way >> to choose right one with assigned-parent-clocks. >> >> I have patchset ready for adding A20 mali node, but I need some more >> time to complete with OPP, then I will submit entire patchset. >> >> Now it works correctly, using right pll(dedicated PLL8), setting >> right frequency. > > The point is that we really don't care about which PLL is actually > being used, as long as the rate is correct and we don't break anything > else. If the GPU rate is accessible through one of the other PLL, it > makes even more sense to not use the GPU PLL and keep it disabled, > since it will result in some power savings. Ah! I see the point now, very clever system for power saving. I'm going to check if it's resolutive, but it sounds good. > >> Btw, do I need to add a board using it, or can I add only Mali node >> to sun7i-a20.dtsi(plus other little patches)? > > You can add it to the DTSI without a board using it (and actually, > nothing should be in the board DTS, everything in the DT for the Mali > applies to all boards). Sure. So I would also add the patch you've addressed me: http://code.bulix.org/1kitrq-268936?raw as a commit. Can I submit it in patchset to complete the whole job? > > Maxime > -- Giulio Benetti R&D Manager & Advanced Research MICRONOVA SRL Sede: Via A. Niedda 3 - 35010 Vigonza (PD) Tel. 049/8931563 - Fax 049/8931346 Cod.Fiscale - P.IVA 02663420285 Capitale Sociale ? 26.000 i.v. Iscritta al Reg. Imprese di Padova N. 02663420285 Numero R.E.A. 258642