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[209.132.180.67]) by mx.google.com with ESMTP id u69si1521060pgb.10.2018.02.02.06.15.15; Fri, 02 Feb 2018 06:15:29 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=E+9iZBqD; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752114AbeBBOOH (ORCPT + 99 others); Fri, 2 Feb 2018 09:14:07 -0500 Received: from fllnx210.ext.ti.com ([198.47.19.17]:18890 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752172AbeBBONx (ORCPT ); Fri, 2 Feb 2018 09:13:53 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id w12ECoE0017107; Fri, 2 Feb 2018 08:12:50 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517580770; bh=GMH5tum1e0BRz0Etr8phOzvT2OcSSrDKbfUHQIia2Wo=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=E+9iZBqDZw+qiidvCmoGNK231C87P8I5n8mKWHICxEHELop8JbUs4QdBHoDoz4oka LFyo0cnh/FH7I+ET/dNMmxvQy60wyqfbIV5ofql1uJSmz/7k8u8NcXOsXRF/5V900U uglSYyUEdvtu5ZYy6Mdh51yWYNbsfNuPolH/LVlU= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w12ECooE021890; Fri, 2 Feb 2018 08:12:50 -0600 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Fri, 2 Feb 2018 08:12:49 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Fri, 2 Feb 2018 08:12:49 -0600 Received: from [172.24.190.171] (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w12ECgBe014545; Fri, 2 Feb 2018 08:12:43 -0600 Subject: Re: [PATCH v6 20/41] ARM: da830: add new clock init using common clock framework To: David Lechner , , , CC: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Kevin Hilman , Bartosz Golaszewski , Adam Ford , References: <1516468460-4908-1-git-send-email-david@lechnology.com> <1516468460-4908-21-git-send-email-david@lechnology.com> From: Sekhar Nori Message-ID: <4b2f45f5-7f0d-f0e6-6854-9992e19f45f2@ti.com> Date: Fri, 2 Feb 2018 19:42:42 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: <1516468460-4908-21-git-send-email-david@lechnology.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Saturday 20 January 2018 10:43 PM, David Lechner wrote: > void __init da830_init_time(void) > { > +#ifdef CONFIG_COMMON_CLK > + void __iomem *pll0, *psc0, *psc1; > + struct clk *clk; > + > + pll0 = ioremap(DA8XX_PLL0_BASE, SZ_4K); > + psc0 = ioremap(DA8XX_PSC0_BASE, SZ_4K); > + psc1 = ioremap(DA8XX_PSC1_BASE, SZ_4K); > + > + da8xx_register_cfgchip(); > + > + clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA830_REF_FREQ); > + > + da830_pll_clk_init(pll0); > + > + da830_psc_clk_init(psc0, psc1); > + > + clk = clk_register_fixed_factor(NULL, "i2c0", "pll0_aux_clk", 0, 1, 1); > + clk_register_clkdev(clk, NULL, "i2c_davinci.1"); > + > + clk = clk_register_fixed_factor(NULL, "timer0", "pll0_aux_clk", 0, 1, 1); > + clk_register_clkdev(clk, "timer0", NULL); > + > + clk = clk_register_fixed_factor(NULL, "timer1", "pll0_aux_clk", 0, 1, 1); > + clk_register_clkdev(clk, NULL, "davinci-wdt"); Isn't this better done in da830_pll_clk_init() ? I think we can get rid of the dummy fixed factor clock too and directly use the pll0_auxclk. That reminds me, is "pll0_aux_clk" above correct, or should it be "pll0_auxclk" like in da830_pll_clk_init()? > + > + clk = clk_register_fixed_factor(NULL, "rmii", "pll0_sysclk7", 0, 1, 1); > + clk_register_clkdev(clk, "rmii", NULL); I don't see any driver looking for this clock using con_id "rmii". I know this came from existing code. But its most likely a vestige and can be dropped. Thanks, Sekhar