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[209.132.180.67]) by mx.google.com with ESMTP id 94-v6si1925750ple.298.2018.02.02.06.38.17; Fri, 02 Feb 2018 06:38:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=LziFtsx7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752140AbeBBOhj (ORCPT + 99 others); Fri, 2 Feb 2018 09:37:39 -0500 Received: from fllnx209.ext.ti.com ([198.47.19.16]:29520 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751643AbeBBOhc (ORCPT ); Fri, 2 Feb 2018 09:37:32 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w12EaSf3018930; Fri, 2 Feb 2018 08:36:28 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517582188; bh=debkh4F6VkWNfBZCbVIuRdRozavQ1SYaUyKoSLDHAtw=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=LziFtsx7SfUaDFrcJhKftyTV1VR0WGjCGsxJC9PFmxFn6wMbvTXZXyNw3NJpxDKIq nKWiqKKgYzRchHs2cEU+hwofF9Fc6fcK6dgN5ESVKqy3I4zQWPFFoZ/aBCVrSJTCIb ExZJz+qFjcF6VQKb+9UrRj2CTL96AOKZcH05xYHs= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w12EaSP8023163; Fri, 2 Feb 2018 08:36:28 -0600 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Fri, 2 Feb 2018 08:36:28 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Fri, 2 Feb 2018 08:36:28 -0600 Received: from [172.24.190.171] (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w12EaMJK031118; Fri, 2 Feb 2018 08:36:23 -0600 Subject: Re: [PATCH v6 22/41] ARM: dm355: add new clock init using common clock framework To: David Lechner , , , CC: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Kevin Hilman , Bartosz Golaszewski , Adam Ford , References: <1516468460-4908-1-git-send-email-david@lechnology.com> <1516468460-4908-23-git-send-email-david@lechnology.com> From: Sekhar Nori Message-ID: <9a0472ad-c76b-7868-e2f8-abbd41659d18@ti.com> Date: Fri, 2 Feb 2018 20:06:22 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: <1516468460-4908-23-git-send-email-david@lechnology.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Saturday 20 January 2018 10:44 PM, David Lechner wrote: > This adds the new board-specific clock init in mach-davinci/dm355.c > using the new common clock framework drivers. > > The #ifdefs are needed to prevent compile errors until the entire > ARCH_DAVINCI is converted. > > Also clean up the #includes since we are adding some here. > > Signed-off-by: David Lechner Reviewed-by: Sekhar Nori Thanks, Sekhar