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Date:   Fri, 2 Feb 2018 16:52:52 +0100
From:   Maxime Ripard <maxime.ripard@bootlin.com>
To:     Giulio Benetti <giulio.benetti@micronovasrl.com>
Cc:     Chen-Yu Tsai <wens@csie.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@codeaurora.org>,
        linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH] clk: sunxi-ng: ccu-sun4i-a10: Fix mali changing dclk
 frequency
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On Fri, Feb 02, 2018 at 04:38:13PM +0100, Giulio Benetti wrote:
> Hi,
>=20
> Il 02/02/2018 14:35, Maxime Ripard ha scritto:
> > On Fri, Feb 02, 2018 at 11:57:20AM +0100, Giulio Benetti wrote:
> > > Il 02/02/2018 11:53, Maxime Ripard ha scritto:
> > > > Hi,
> > > >=20
> > > > On Thu, Feb 01, 2018 at 05:17:11PM +0100, Giulio Benetti wrote:
> > > > > > > > What kernel version did you use?
> > > > > > >=20
> > > > > > > Latest mainline.
> > > > > >=20
> > > > > > I guess this patch could fix it:
> > > > > > http://code.bulix.org/1kitrq-268936?raw
> > > > >=20
> > > > > This should prevent from modifying parent clock. But my problem w=
as
> > > > > different.
> > > > >=20
> > > > > On A20, gpu_clk can have different PLL, not I've found out the way
> > > > > to choose right one with assigned-parent-clocks.
> > > > >=20
> > > > > I have patchset ready for adding A20 mali node, but I need some m=
ore
> > > > > time to complete with OPP, then I will submit entire patchset.
> > > > >=20
> > > > > Now it works correctly, using right pll(dedicated PLL8), setting
> > > > > right frequency.
> > > >=20
> > > > The point is that we really don't care about which PLL is actually
> > > > being used, as long as the rate is correct and we don't break anyth=
ing
> > > > else. If the GPU rate is accessible through one of the other PLL, it
> > > > makes even more sense to not use the GPU PLL and keep it disabled,
> > > > since it will result in some power savings.
> > >=20
> > > Ah! I see the point now, very clever system for power saving.
> > > I'm going to check if it's resolutive,
> > > but it sounds good.
> > >=20
> > > >=20
> > > > > Btw, do I need to add a board using it, or can I add only Mali no=
de
> > > > > to sun7i-a20.dtsi(plus other little patches)?
> > > >=20
> > > > You can add it to the DTSI without a board using it (and actually,
> > > > nothing should be in the board DTS, everything in the DT for the Ma=
li
> > > > applies to all boards).
> > >=20
> > > Sure. So I would also add the patch you've addressed me:
> > > http://code.bulix.org/1kitrq-268936?raw
> > > as a commit. Can I submit it in patchset to complete the whole job?
> >=20
> > I already sent that patch quite some time ago, I'll just apply it. You
> > can send the DT patch :)
>=20
> Thanks. Sorry for my ignorance, but where are you applying patches?
> Because I've tried to check sunxi-next and a lot of other Repo but I can't
> find this and neither "Re: [PATCH] clk: sunxi-ng: ccu-sun4i-a10: Fix mali
> changing dclk frequency"

Usually, in the git tree listed in MAINTAINERS :)

Maxime

--=20
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com

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