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Subject: Re: [PATCH] clk: sunxi-ng: ccu-sun4i-a10: Fix mali changing dclk
 frequency
To:     Maxime Ripard <maxime.ripard@bootlin.com>
Cc:     Chen-Yu Tsai <wens@csie.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@codeaurora.org>,
        linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
        linux-kernel@vger.kernel.org
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From:   Giulio Benetti <giulio.benetti@micronovasrl.com>
Message-ID: <eaeec60a-5f9a-58f6-7d1c-9877c729fe34@micronovasrl.com>
Date:   Fri, 2 Feb 2018 23:46:21 +0100
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Il 02/02/2018 22:59, Maxime Ripard ha scritto:
> On Fri, Feb 02, 2018 at 06:21:18PM +0100, Giulio Benetti wrote:
>> Hi,
>>
>> Il 02/02/2018 16:52, Maxime Ripard ha scritto:
>>> On Fri, Feb 02, 2018 at 04:38:13PM +0100, Giulio Benetti wrote:
>>>> Hi,
>>>>
>>>> Il 02/02/2018 14:35, Maxime Ripard ha scritto:
>>>>> On Fri, Feb 02, 2018 at 11:57:20AM +0100, Giulio Benetti wrote:
>>>>>> Il 02/02/2018 11:53, Maxime Ripard ha scritto:
>>>>>>> Hi,
>>>>>>>
>>>>>>> On Thu, Feb 01, 2018 at 05:17:11PM +0100, Giulio Benetti wrote:
>>>>>>>>>>> What kernel version did you use?
>>>>>>>>>>
>>>>>>>>>> Latest mainline.
>>>>>>>>>
>>>>>>>>> I guess this patch could fix it:
>>>>>>>>> http://code.bulix.org/1kitrq-268936?raw
>>>>>>>>
>>>>>>>> This should prevent from modifying parent clock. But my problem was
>>>>>>>> different.
>>>>>>>>
>>>>>>>> On A20, gpu_clk can have different PLL, not I've found out the way
>>>>>>>> to choose right one with assigned-parent-clocks.
>>>>>>>>
>>>>>>>> I have patchset ready for adding A20 mali node, but I need some more
>>>>>>>> time to complete with OPP, then I will submit entire patchset.
>>>>>>>>
>>>>>>>> Now it works correctly, using right pll(dedicated PLL8), setting
>>>>>>>> right frequency.
>>>>>>>
>>>>>>> The point is that we really don't care about which PLL is actually
>>>>>>> being used, as long as the rate is correct and we don't break anything
>>>>>>> else. If the GPU rate is accessible through one of the other PLL, it
>>>>>>> makes even more sense to not use the GPU PLL and keep it disabled,
>>>>>>> since it will result in some power savings.
>>>>>>
>>>>>> Ah! I see the point now, very clever system for power saving.
>>>>>> I'm going to check if it's resolutive,
>>>>>> but it sounds good.
>>>>>>
>>>>>>>
>>>>>>>> Btw, do I need to add a board using it, or can I add only Mali node
>>>>>>>> to sun7i-a20.dtsi(plus other little patches)?
>>>>>>>
>>>>>>> You can add it to the DTSI without a board using it (and actually,
>>>>>>> nothing should be in the board DTS, everything in the DT for the Mali
>>>>>>> applies to all boards).
>>>>>>
>>>>>> Sure. So I would also add the patch you've addressed me:
>>>>>> http://code.bulix.org/1kitrq-268936?raw
>>>>>> as a commit. Can I submit it in patchset to complete the whole job?
>>>>>
>>>>> I already sent that patch quite some time ago, I'll just apply it. You
>>>>> can send the DT patch :)
>>>>
>>>> Thanks. Sorry for my ignorance, but where are you applying patches?
>>>> Because I've tried to check sunxi-next and a lot of other Repo but I can't
>>>> find this and neither "Re: [PATCH] clk: sunxi-ng: ccu-sun4i-a10: Fix mali
>>>> changing dclk frequency"
>>>
>>> Usually, in the git tree listed in MAINTAINERS :)
>>
>> Please don't laugh at me! :)
>>
>> I've tried to check for your patch(drivers/gpu/drm/sun4i/sun4i_tcon.c) on:
>> https://cgit.freedesktop.org/drm/drm-misc/
>> according to MAINTAINERS file and nothing found.
> 
> I haven't applied that one yet, so it's not suprising :)

Ah ok!

> 
>> For the other one(arch/arm/boot/dts/sun7i-a20.dtsi), I've checked
>> on:
>> https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git/
>> https://git.kernel.org/pub/scm/linux/kernel/git/device-mapper/linux-dm.git/
>> https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/
>>
>> Nothing neither here!
>>
>> In MAINTANERS file there's no arch/arm/boot/dts/sun* association.
> 
> I forgot to push that one:
> https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git/log/?h=sunxi/dt-for-4.17

Thank god! I haven't gone nut!! :))
I think I've understood how it works this part.

Thanks!!!

Thanks

> 
> Maxime
> 


-- 
Giulio Benetti
R&D Manager &
Advanced Research

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