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[209.132.180.67]) by mx.google.com with ESMTP id i1si2826925pgo.426.2018.02.03.03.24.25; Sat, 03 Feb 2018 03:24:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=SopUuN1L; dkim=pass header.i=@codeaurora.org header.s=default header.b=SopUuN1L; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751956AbeBCLRo (ORCPT + 99 others); Sat, 3 Feb 2018 06:17:44 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:44714 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750744AbeBCLRk (ORCPT ); Sat, 3 Feb 2018 06:17:40 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 62CD56090E; Sat, 3 Feb 2018 11:17:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1517656659; bh=qujb9q6mGwVsVnbsgVzY1YgZQSBk1pjf59zHm3Ct1x4=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=SopUuN1Lr5KQzQeZK9NF6YBscg0QQr2wCx+EYWe4gR2+rOtPzk/hJd2VzkYgesrvR ElEAHVRSzMUXhfX9lGLJVa/5RO4WYOadgOFvlAfaqAKN0Val9cRAk3aurciIwHMMIh v6ZxaFieGREwbDWL4JS/5UMVFOohNMRCBScs8JXE= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 07083606AC; Sat, 3 Feb 2018 11:17:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1517656659; bh=qujb9q6mGwVsVnbsgVzY1YgZQSBk1pjf59zHm3Ct1x4=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=SopUuN1Lr5KQzQeZK9NF6YBscg0QQr2wCx+EYWe4gR2+rOtPzk/hJd2VzkYgesrvR ElEAHVRSzMUXhfX9lGLJVa/5RO4WYOadgOFvlAfaqAKN0Val9cRAk3aurciIwHMMIh v6ZxaFieGREwbDWL4JS/5UMVFOohNMRCBScs8JXE= MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Sat, 03 Feb 2018 16:47:39 +0530 From: Abhishek Sahu To: Sricharan R Cc: robh+dt@kernel.org, robh@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, andy.gross@linaro.org, david.brown@linaro.org, catalin.marinas@arm.com, will.deacon@arm.com, sboyd@codeaurora.org, bjorn.andersson@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-arm-msm-owner@vger.kernel.org Subject: Re: [PATCH 06/15] ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi In-Reply-To: <1517202689-14212-7-git-send-email-sricharan@codeaurora.org> References: <1517202689-14212-1-git-send-email-sricharan@codeaurora.org> <1517202689-14212-7-git-send-email-sricharan@codeaurora.org> Message-ID: X-Sender: absahu@codeaurora.org User-Agent: Roundcube Webmail/1.2.5 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2018-01-29 10:41, Sricharan R wrote: > Add the common parts for the dk04 boards. > > Signed-off-by: Sricharan R > --- > arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 147 > + > + nand_pins: nand_pins { > + pullups { > + pins = "gpio52", "gpio53", > "gpio58", > + "gpio59"; > + function = "qpic"; > + bias-pull-up; > + }; > + > + pulldowns { > + pins = "gpio54", "gpio55", > "gpio56", > + "gpio57", "gpio60", > "gpio61", > + "gpio62", "gpio63", > "gpio64", > + "gpio65", "gpio66", > "gpio67", > + "gpio68", "gpio69"; > + function = "qpic"; > + bias-pull-down; > + }; > + }; Can you please check once why do we need pull-up and pull-down for NAND pins. The NAND chip will be mounted over board itself so board design should take care of required pull up and pull downs. Also, some of the above pins like gpio52 will be only used for LCD so we can remove those pins. Later on, when LCD support will be added, we can add those pins. Thanks, Abhishek