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Date:   Mon, 5 Feb 2018 14:11:11 +0000
From:   James Hogan <jhogan@kernel.org>
To:     Matt Redfearn <matt.redfearn@mips.com>
Cc:     Ralf Baechle <ralf@linux-mips.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        linux-mips@linux-mips.org, Paul Burton <paul.burton@mips.com>,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/6] MIPS: Generic: Support GIC in EIC mode
Message-ID: <20180205141110.GC8479@saruman>
References: <1515148270-9391-1-git-send-email-matt.redfearn@mips.com>
 <1515148270-9391-4-git-send-email-matt.redfearn@mips.com>
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On Fri, Jan 05, 2018 at 10:31:07AM +0000, Matt Redfearn wrote:
> The GIC supports running in External Interrupt Controller (EIC) mode,
> and will signal this via cpu_has_veic if enabled in hardware. Currently
> the generic kernel will panic if cpu_has_veic is set - but the GIC can
> legitimately set this flag if either configured to boot in EIC mode, or
> if the GIC driver enables this mode. Make the kernel not panic in this
> case, and instead just check if the GIC is present. If so, use it's CPU
> local interrupt routing functions. If an EIC is present, but it is not
> the GIC, then the kernel does not know how to get the VIRQ for the CPU
> local interrupts and should panic. Support for alternative EICs being
> present is needed here for the generic kernel to support them.
>=20
> Suggested-by: Paul Burton <paul.burton@mips.com>
> Signed-off-by: Matt Redfearn <matt.redfearn@mips.com>

Applied for 4.16,

Thanks
James

> ---
>=20
>  arch/mips/generic/irq.c | 18 +++++++++---------
>  1 file changed, 9 insertions(+), 9 deletions(-)
>=20
> diff --git a/arch/mips/generic/irq.c b/arch/mips/generic/irq.c
> index 394f8161e462..cb7fdaeef426 100644
> --- a/arch/mips/generic/irq.c
> +++ b/arch/mips/generic/irq.c
> @@ -22,10 +22,10 @@ int get_c0_fdc_int(void)
>  {
>  	int mips_cpu_fdc_irq;
> =20
> -	if (cpu_has_veic)
> -		panic("Unimplemented!");
> -	else if (mips_gic_present())
> +	if (mips_gic_present())
>  		mips_cpu_fdc_irq =3D gic_get_c0_fdc_int();
> +	else if (cpu_has_veic)
> +		panic("Unimplemented!");
>  	else if (cp0_fdc_irq >=3D 0)
>  		mips_cpu_fdc_irq =3D MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
>  	else
> @@ -38,10 +38,10 @@ int get_c0_perfcount_int(void)
>  {
>  	int mips_cpu_perf_irq;
> =20
> -	if (cpu_has_veic)
> -		panic("Unimplemented!");
> -	else if (mips_gic_present())
> +	if (mips_gic_present())
>  		mips_cpu_perf_irq =3D gic_get_c0_perfcount_int();
> +	else if (cpu_has_veic)
> +		panic("Unimplemented!");
>  	else if (cp0_perfcount_irq >=3D 0)
>  		mips_cpu_perf_irq =3D MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
>  	else
> @@ -54,10 +54,10 @@ unsigned int get_c0_compare_int(void)
>  {
>  	int mips_cpu_timer_irq;
> =20
> -	if (cpu_has_veic)
> -		panic("Unimplemented!");
> -	else if (mips_gic_present())
> +	if (mips_gic_present())
>  		mips_cpu_timer_irq =3D gic_get_c0_compare_int();
> +	else if (cpu_has_veic)
> +		panic("Unimplemented!");
>  	else
>  		mips_cpu_timer_irq =3D MIPS_CPU_IRQ_BASE + cp0_compare_irq;
> =20
> --=20
> 2.7.4
>=20
>=20

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