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[209.132.180.67]) by mx.google.com with ESMTP id a6-v6si4129952pll.495.2018.02.05.22.03.18; Mon, 05 Feb 2018 22:03:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=lSeOXRDP; dkim=pass header.i=@codeaurora.org header.s=default header.b=j2NCr0O5; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751424AbeBFGB1 (ORCPT + 99 others); Tue, 6 Feb 2018 01:01:27 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:58678 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750841AbeBFGBT (ORCPT ); Tue, 6 Feb 2018 01:01:19 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 8BC6160A06; Tue, 6 Feb 2018 06:01:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1517896878; bh=2LF5OSObBQabLrPgcHu7kELo49Af8lgCkQtfDQb1mZY=; h=Subject:To:Cc:References:From:Date:In-Reply-To:From; b=lSeOXRDP8PvOPwRhTVZoB5J5wq7BeiO5/IcuaKaiLa1mx4mjPzGfD5CsDpXaxd7Zz wu0GxoR6r7iwVKtvVO0nndrqPRdmn1DRZMjFpiJvDV7IqTHfdneYyr4y74t4wojSv5 ildh4sDKJajQM5ojex4toQDnjii4I0SXZUuYLY1U= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from [10.201.3.39] (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sricharan@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 23AFB6014B; Tue, 6 Feb 2018 06:01:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1517896877; bh=2LF5OSObBQabLrPgcHu7kELo49Af8lgCkQtfDQb1mZY=; h=Subject:To:Cc:References:From:Date:In-Reply-To:From; b=j2NCr0O53D+PNxrLTtISSywqjOOpMS8bbotLInDnkWepB+t53ZRSpGm4ub4Qp204N 3JCmzDx1CZgHx2aRnarHK06nlvx70ojA4i2Vauz/EDxvrRSDBGJLjjmyoih7XwfGqF EO/lWb+7p3hT6gW/q7Um0HErED8LQpQsat2rJoaY= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 23AFB6014B Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sricharan@codeaurora.org Subject: Re: [PATCH 06/15] ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi To: Abhishek Sahu Cc: mark.rutland@arm.com, robh@kernel.org, devicetree@vger.kernel.org, catalin.marinas@arm.com, will.deacon@arm.com, linux@armlinux.org.uk, bjorn.andersson@linaro.org, david.brown@linaro.org, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, andy.gross@linaro.org, linux-arm-msm-owner@vger.kernel.org, linux-soc@vger.kernel.org, sboyd@codeaurora.org, linux-kernel@vger.kernel.org References: <1517202689-14212-1-git-send-email-sricharan@codeaurora.org> <1517202689-14212-7-git-send-email-sricharan@codeaurora.org> From: Sricharan R Message-ID: <65ec9aef-c712-b8de-8da0-c1211ea0fbb3@codeaurora.org> Date: Tue, 6 Feb 2018 11:31:10 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Abhishek, On 2/3/2018 4:47 PM, Abhishek Sahu wrote: > On 2018-01-29 10:41, Sricharan R wrote: >> Add the common parts for the dk04 boards. >> >> Signed-off-by: Sricharan R >> --- >>  arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 147 > >   >> + >> +            nand_pins: nand_pins { >> +                pullups { >> +                    pins = "gpio52", "gpio53", >> "gpio58", >> +                        "gpio59"; >> +                    function = "qpic"; >> +                    bias-pull-up; >> +                }; >> + >> +                pulldowns { >> +                    pins = "gpio54", "gpio55", >> "gpio56", >> +                        "gpio57", "gpio60", >> "gpio61", >> +                        "gpio62", "gpio63", >> "gpio64", >> +                        "gpio65", "gpio66", >> "gpio67", >> +                        "gpio68", "gpio69"; >> +                    function = "qpic"; >> +                    bias-pull-down; >> +                }; >> +            }; > >  Can you please check once why do we need pull-up and >  pull-down for NAND pins. The NAND chip will be mounted >  over board itself so board design should take care of >  required pull up and pull downs. > Mostly because, these are always **weak** pull up/down as defaults and should be overridden by the ones in the board (if there). >  Also, some of the above pins like gpio52 will be only used >  for LCD so we can remove those pins. Later on, when LCD >  support will be added, we can add those pins. ok Regards, Sricharan -- "QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation