Received: by 10.223.176.5 with SMTP id f5csp350022wra; Mon, 5 Feb 2018 23:29:54 -0800 (PST) X-Google-Smtp-Source: AH8x226e5YzWpp5PMYBvM6LtnwwTlh/iWd9dDOGjQ2Bacc6zDpSs1AIwc5HmmpV3XGPTV0QYFj1p X-Received: by 2002:a17:902:8496:: with SMTP id c22-v6mr1527087plo.36.1517902194273; Mon, 05 Feb 2018 23:29:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517902194; cv=none; d=google.com; s=arc-20160816; b=K35e3EWda34gWH2Mt5l+OJ0UDl42nFYZ189/guooS7yUTwRLuGTkTpYFwNOgYp4vi1 XX8iW2F4ZhCpqNzbxqTvcNYQqtRqbJZskgVPAlbi5UJHgxnBx8HLFcdyv8UVHVhLDoOy M0gweseROTx+Rny4pZVVFJR1KmZQvmCsJI7S+0xptC1UXNV4MFIZ+Gbvl3gyQ/DXhAKJ p5QK5ATGdWb6YaPWuWm2bd1kKa5HldtKfLwkGW77Xjff5FW72iX3XvEWc9Ob0f4N11zJ aLVfFhMoEPlC6hWDPlnCjPkCHl103pcNPWwhMmOLYZtyIwhvcAt10zNFOijTlU8q0I84 V8cQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=/9xlUKN14enTDf0eq9fPYMbTE7N7xA1mUfiDK26o5Ek=; b=nyPR+JdbB5HjTD2fp3evTjXwkiWhXZ0xl96LXuIweGwQHdBlhC/W5u9G5Co/9k3Ab7 Px1FI1iLx89Jw3rIQZ/VeWwcIxOK1d6hycVr13sYOYra3p/kL041LW2TsUBXPQRYj1lS B+Bb7NvH24yUkZGbAP3Y51fTbHjL4xtDkqcX9aBfAPApQEN/aTi2TUBOC2XWXK4dOsch /z1QXVLJe5dESJ4SZ3G05AiluuivGCoRTD2Etfx/wvcwlFPdZTWUo3z94wr2RNBI/cFZ fiZkUxIehBVqwQCwdUIcIYUV3XJYIipXvf+VfHhKpyZNG0uGCm7+v2RvUegJGXVE5h9x cCfA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g6si6546382pgr.588.2018.02.05.23.29.39; Mon, 05 Feb 2018 23:29:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751835AbeBFH2y (ORCPT + 99 others); Tue, 6 Feb 2018 02:28:54 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:6242 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752364AbeBFH2V (ORCPT ); Tue, 6 Feb 2018 02:28:21 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Mon, 05 Feb 2018 23:28:26 -0800 Received: from HQMAIL104.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 05 Feb 2018 23:28:20 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 05 Feb 2018 23:28:20 -0800 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 6 Feb 2018 07:28:20 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server id 15.0.1347.2 via Frontend Transport; Tue, 6 Feb 2018 07:28:20 +0000 Received: from mperttunen-lnx.Nvidia.com (Not Verified[10.21.26.144]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 05 Feb 2018 23:28:19 -0800 From: Mikko Perttunen To: , , , CC: , , , , , Mikko Perttunen Subject: [PATCH v2 7/7] arm64: tegra: Add device tree for the Tegra194 P2972-0000 board Date: Tue, 6 Feb 2018 09:22:37 +0200 Message-ID: <1517901757-15353-8-git-send-email-mperttunen@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1517901757-15353-1-git-send-email-mperttunen@nvidia.com> References: <1517901757-15353-1-git-send-email-mperttunen@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add device tree files for the Tegra194 P2972-0000 development board. The board consists of the P2888 compute module and the P2822 baseboard. Signed-off-by: Mikko Perttunen --- arch/arm64/boot/dts/nvidia/Makefile | 1 + arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 248 +++++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 16 ++ 3 files changed, 265 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi create mode 100644 arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile index 676aa2f238d1..7c13d7df484e 100644 --- a/arch/arm64/boot/dts/nvidia/Makefile +++ b/arch/arm64/boot/dts/nvidia/Makefile @@ -5,3 +5,4 @@ dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb +dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p2972-0000.dtb diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi new file mode 100644 index 000000000000..ecb034177fc2 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -0,0 +1,248 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "tegra194.dtsi" + +#include + +/ { + model = "NVIDIA Tegra194 P2888 Processor Module"; + compatible = "nvidia,p2888", "nvidia,tegra194"; + + aliases { + sdhci0 = "/cbb/sdhci@3460000"; + sdhci1 = "/cbb/sdhci@3400000"; + serial0 = &uartb; + i2c0 = "/bpmp/i2c"; + i2c1 = "/cbb/i2c@3160000"; + i2c2 = "/cbb/i2c@c240000"; + i2c3 = "/cbb/i2c@3180000"; + i2c4 = "/cbb/i2c@3190000"; + i2c5 = "/cbb/i2c@31c0000"; + i2c6 = "/cbb/i2c@c250000"; + i2c7 = "/cbb/i2c@31e0000"; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = "serial0:115200n8"; + }; + + cbb { + serial@3110000 { + status = "okay"; + }; + + /* SDMMC1 (SD/MMC) */ + sdhci@3400000 { +/* + cd-gpios = <&gpio TEGRA194_MAIN_GPIO(A, 0) GPIO_ACTIVE_LOW>; +*/ + }; + + /* SDMMC4 (eMMC) */ + sdhci@3460000 { + status = "okay"; + bus-width = <8>; + non-removable; + + vqmmc-supply = <&vdd_1v8ls>; + vmmc-supply = <&vdd_emmc_3v3>; + }; + + pmc@c360000 { + nvidia,invert-interrupt; + }; + }; + + bpmp { + i2c { + status = "okay"; + + pmic: pmic@3c { + compatible = "maxim,max20024"; + reg = <0x3c>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + + #gpio-cells = <2>; + gpio-controller; + + pinctrl-names = "default"; + pinctrl-0 = <&max20024_default>; + + max20024_default: pinmux { + gpio0 { + pins = "gpio0"; + function = "gpio"; + }; + + gpio1 { + pins = "gpio1"; + function = "fps-out"; + maxim,active-fps-source = ; + }; + + gpio2 { + pins = "gpio2"; + function = "fps-out"; + maxim,active-fps-source = ; + }; + + gpio3 { + pins = "gpio3"; + function = "fps-out"; + maxim,active-fps-source = ; + }; + + gpio4 { + pins = "gpio4"; + function = "32k-out1"; + drive-push-pull = <1>; + }; + + gpio6 { + pins = "gpio6"; + function = "gpio"; + drive-push-pull = <1>; + }; + + gpio7 { + pins = "gpio7"; + function = "gpio"; + drive-push-pull = <0>; + }; + }; + + fps { + fps0 { + maxim,fps-event-source = ; + maxim,shutdown-fps-time-period-us = <640>; + }; + + fps1 { + maxim,fps-event-source = ; + maxim,shutdown-fps-time-period-us = <640>; + maxim,device-state-on-disabled-event = ; + }; + + fps2 { + maxim,fps-event-source = ; + maxim,shutdown-fps-time-period-us = <640>; + }; + }; + + regulators { + in-sd0-supply = <&vdd_5v0_sys>; + in-sd1-supply = <&vdd_5v0_sys>; + in-sd2-supply = <&vdd_5v0_sys>; + in-sd3-supply = <&vdd_5v0_sys>; + in-sd4-supply = <&vdd_5v0_sys>; + + in-ldo0-1-supply = <&vdd_5v0_sys>; + in-ldo2-supply = <&vdd_5v0_sys>; + in-ldo3-5-supply = <&vdd_5v0_sys>; + in-ldo4-6-supply = <&vdd_5v0_sys>; + in-ldo7-8-supply = <&vdd_1v8ls>; + + sd0 { + regulator-name = "VDD_1V0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + sd1 { + regulator-name = "VDD_1V8HS"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v8ls: sd2 { + regulator-name = "VDD_1V8LS"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + sd3 { + regulator-name = "VDD_1V8AO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + sd4 { + regulator-name = "VDD_DDR_1V1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo0 { + regulator-name = "VDD_RTC"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo2 { + regulator-name = "VDD_AO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_emmc_3v3: ldo3 { + regulator-name = "VDD_EMMC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo5 { + regulator-name = "VDD_USB_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo6 { + regulator-name = "VDD_SDIO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo7 { + regulator-name = "VDD_CSI_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + }; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_5v0_sys: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + + regulator-name = "VIN_SYS_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts new file mode 100644 index 000000000000..9ff3c18280c4 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra194-p2888.dtsi" + +/ { + model = "NVIDIA Tegra194 P2972-0000 Development Board"; + compatible = "nvidia,p2972-0000", "nvidia,tegra194"; + + cbb { + /* SDMMC1 (SD/MMC) */ + sdhci@3400000 { + status = "okay"; + }; + }; +}; -- 2.1.4