Received: by 10.223.176.5 with SMTP id f5csp466313wra; Tue, 6 Feb 2018 01:58:04 -0800 (PST) X-Google-Smtp-Source: AH8x2253swxVvldN7qcx8TGkJVA/maVsX6bILt7ZLA/Zg1MTM2UDh3OF41iP7aQg16CvwB3JWviK X-Received: by 10.99.167.14 with SMTP id d14mr1545266pgf.150.1517911084324; Tue, 06 Feb 2018 01:58:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517911084; cv=none; d=google.com; s=arc-20160816; b=kUP8rL/vf7TvhBZGsp65Ia1vsb48FWC7spdH8pqy66/4g+J+MYJd7+o2QlYlQtEAZJ EPcxRq2C58OOHW9TNEO6AlRysiSXhDyMBxWcEgscIvx+4vv2yMfX+KcB9sEHBJth5BN+ ORLdpDvwncJFD9yxwj1k2dyQpHXBaLZIW9uTl0MRHUUUffBLNgR0gTn+Pz5ARlVOTDul fy8Y83Z8Y3SKt1LVaJ+cadsu9l2/NCLWkIn4UsTAKwLgUm45M5+u//gQgh6b4maNTy2Q TiZgcOf4pE4UeeDcfmgeaNrOc9D2W78GWR6dbyl5RPgt75jtd+jNBEkj1VFuKr0F3Kd2 huVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=JrapJKMGow/3tvoKXa9tYa89LskKP4eseSVfqEQF7Vc=; b=Kl+Yt21hWcTvYOGVHzF+sZzZrCxQFaEBKktO4LQ+RyEQsBlLuEED12/777cjOlmEju Lhc0vLYSKmwWjl4xnJba6nNZLPE0Vb4hyh9Cy+AYLWFj8Z2A/TqIDq1v4eE3Zysg3OO3 9kVhvQmlUiOtZCXo/JBMgq4lNiv9ru1nlXoHi58aAOpaBhTGlbiTJUb2YnxQNhznGVvV /m9VY9KVH45xItIGjw8In4FwvcYLUIS+fpHQ3AYn/LDe4chqhaiaVzACskQmVDpvdSj8 GRrO39hg1L1TgfflvGeIXemZO4GzsdwlgGzGM5V+Y9ThDu+7/7eQPBpxiwUU1705/wg+ 8nQg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 44-v6si969849plb.40.2018.02.06.01.57.49; Tue, 06 Feb 2018 01:58:04 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752942AbeBFJ4M (ORCPT + 99 others); Tue, 6 Feb 2018 04:56:12 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:44470 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752669AbeBFJxZ (ORCPT ); Tue, 6 Feb 2018 04:53:25 -0500 X-UUID: d8cff251467d4b21b1e98281d5b6f6b1-20180206 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1196142334; Tue, 06 Feb 2018 17:53:21 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 6 Feb 2018 17:53:20 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Tue, 6 Feb 2018 17:53:20 +0800 From: To: , , , , CC: , , Sean Wang Subject: [PATCH v2 07/16] arm64: dts: mt7622: turn uart0 clock to real ones Date: Tue, 6 Feb 2018 17:52:56 +0800 Message-ID: X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sean Wang This patch also cleans up two oscillators that provide clocks for MT7623. Switch the uart clocks to the real ones while at it. Signed-off-by: Sean Wang Cc: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 65eb417..845fc11 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -88,18 +88,6 @@ }; }; - uart_clk: dummy25m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - bus_clk: dummy280m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <280000000>; - }; - pwrap_clk: dummy40m { compatible = "fixed-clock"; clock-frequency = <40000000>; @@ -231,7 +219,8 @@ "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x400>; interrupts = ; - clocks = <&uart_clk>, <&bus_clk>; + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&pericfg CLK_PERI_UART1_PD>; clock-names = "baud", "bus"; status = "disabled"; }; -- 2.7.4