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[209.132.180.67]) by mx.google.com with ESMTP id g1-v6si1127172plk.422.2018.02.06.05.54.24; Tue, 06 Feb 2018 05:54:38 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=vA6LC1AO; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752100AbeBFNxh (ORCPT + 99 others); Tue, 6 Feb 2018 08:53:37 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:57072 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751995AbeBFNxU (ORCPT ); Tue, 6 Feb 2018 08:53:20 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w16Dq2x7029906; Tue, 6 Feb 2018 07:52:02 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517925122; bh=j2ZS4/dqfpB2o9R9aLoJUGbdo/WGJ/9CS4Q0nJDntEM=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=vA6LC1AOp3PgSDV7IWZdx1WsAStXn9c3SkYHNRDURzI9wLtAYtEq51YhTt5xNpVJn Zu5icl24zvS8Q5C77W3Uv/NjAuxU5xaTfoQAwLnv6C+9eAEEgiTuQ6l/MBMEWoHQCQ lkr4gNSAorhZR0h3DMcSw7D5R3eUcyKA/PHRWwEQ= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w16Dq2eK024407; Tue, 6 Feb 2018 07:52:02 -0600 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 6 Feb 2018 07:52:01 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 6 Feb 2018 07:52:01 -0600 Received: from [172.24.190.171] (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w16Dpthv007687; Tue, 6 Feb 2018 07:51:56 -0600 Subject: Re: [PATCH] ARM: dts: da850-evm: add clock properties to the nand node To: Bartosz Golaszewski CC: Bartosz Golaszewski , Kevin Hilman , Rob Herring , Mark Rutland , Russell King , David Lechner , arm-soc , linux-devicetree , LKML References: <20180205155222.22189-1-brgl@bgdev.pl> <3f171f6a-bcea-65ec-d56d-f6ae24660f34@ti.com> From: Sekhar Nori Message-ID: <54dbdb98-e0e4-c8c9-fec4-2f050745d9be@ti.com> Date: Tue, 6 Feb 2018 19:21:54 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tuesday 06 February 2018 06:38 PM, Bartosz Golaszewski wrote: > 2018-02-06 12:07 GMT+01:00 Sekhar Nori : >> On Monday 05 February 2018 09:22 PM, Bartosz Golaszewski wrote: >>> From: Bartosz Golaszewski >>> >>> Make nand work with the common clock framework by specifying which >>> clock should be used and what name to look up. >>> >>> Signed-off-by: Bartosz Golaszewski >>> --- >>> arch/arm/boot/dts/da850-evm.dts | 3 +++ >>> 1 file changed, 3 insertions(+) >>> >>> diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts >>> index a86a8a1816f2..2602ad8e99ee 100644 >>> --- a/arch/arm/boot/dts/da850-evm.dts >>> +++ b/arch/arm/boot/dts/da850-evm.dts >>> @@ -296,6 +296,9 @@ >>> reg = <0 0x02000000 0x02000000 >>> 1 0x00000000 0x00008000>; >>> >>> + clocks = <&psc0 3>; >>> + clock-names = "aemif"; >> >> Looks like this is being added only to satisfy the devm_clk_get() call >> in nand_davinci_probe() which I think is superfluous since we also >> enable the same clock in aemif_probe(). >> >> Perhaps the better solution is to drip the clk code in >> drivers/mtd/nand/davinci_nand.c and shift legacy code to start using >> drivers/memory/aemif.c as well? This way we can also drop >> arch/arm/mach-davinci/aemif.c >> >> Thanks, >> Sekhar > > Yes, this sounds good, but I think we should leave it for later as an > additional improvement, once everything else is in place. I think > these patches should be applied together with David's series in order > to not break the support on davinci boards and the aemif work would go > in later as a follow-up. How about that? No, I dont think we should add temporary hacks to DT to work around driver issues (I do think its a hack since the clock belongs to aemif module not NAND flash). An easier driver hack might be to not treat devm_clk_get() failure in davinci_nand.c as catastrophic. It will safely fail in DT case and we should get the clock in legacy boot case. I think we are looking at a driver update dependency anyway. > > Also: I don't have any keystone board to test whether such changes > don't break the nand support there. Would you be able to test this? Yes, I have access to those boards. Thanks, Sekhar