Received: by 10.223.176.5 with SMTP id f5csp863957wra; Tue, 6 Feb 2018 08:36:45 -0800 (PST) X-Google-Smtp-Source: AH8x225nT9S98VjGN3yZRNLcE5LLTKnL5rnx4Rz5/rkdzYczJpsa07VsJzTPJhbFD9nvsx+AzO54 X-Received: by 10.99.60.28 with SMTP id j28mr2463941pga.207.1517935005789; Tue, 06 Feb 2018 08:36:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517935005; cv=none; d=google.com; s=arc-20160816; b=emhFmFBceisKkV7feN8RNPUHEpot2ZhcDjoRYgE6FeCiqB1001wUbOmqaTl9TwhM8R QkaaIpiZUdpDPmVgX3aqL1IL1tNA9ogrBY2CqARsCFlnwCgtT4haDeKxzF/UDBEOWNow x/V/CmsS194oevIrvCZIwdexeVB1uxjvJmSRpPDPkM9FnOkbdQgnVasCjHY7+fcJIIX4 vkMpGeDMFY727bvp00uKo973jMQvCQo6Da8qKOaD3uLRb0kw4Sl1IZW9HRSNc3ipo14C ODIOTvcdIxqc4PakWqzrAi/ZyCZFa10fP/AnGjGscSTZ0LsiRPYkOCW0MEljYpCuqP9Y piyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=5Ew4X9psFpmptAAo1kF75YpSraXt5fqjJMWxVd+BayM=; b=QMay05E5Y26aFdL0CsouZP45c4S6reGcbAf+NXXZdJKCfdCmJzqXo07PayZjw3Zomj aD685Wji16S9afdchQTxrzc1Af4nIh4zsO78qg9Sz7UQMiNWpqKWmu1xp60MuQk0Wgyd uVtGIkeCiKSwvVUlpDgKXzny8Eudn6+19SMA+GVzKZx5Wu3p3u/Q4ns3ovoEiGHXt800 o2J9vOTt1wGXB79Wl2tbmKWz6JMmSr9OqxCuJijW4+FC5botjenIGmoT2VvLOnEtUFOa A15AVTGGU1IKZfUj2ZyBW2Ox44ofEHvhYyVnAQ2+d/U6As3CJTciH2R29NgTw6J8F+Tp DZPQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d8-v6si1826937plo.17.2018.02.06.08.36.31; Tue, 06 Feb 2018 08:36:45 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752755AbeBFQfa (ORCPT + 99 others); Tue, 6 Feb 2018 11:35:30 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:18971 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752450AbeBFQet (ORCPT ); Tue, 6 Feb 2018 11:34:49 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Tue, 06 Feb 2018 08:34:50 -0800 Received: from HQMAIL108.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 06 Feb 2018 08:35:28 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 06 Feb 2018 08:35:28 -0800 Received: from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 6 Feb 2018 16:34:45 +0000 Received: from tbergstrom-lnx.Nvidia.com (10.21.24.170) by UKMAIL101.nvidia.com (10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 6 Feb 2018 16:34:38 +0000 Received: from tbergstrom-lnx.nvidia.com (localhost [127.0.0.1]) by tbergstrom-lnx.Nvidia.com (Postfix) with ESMTP id BD1DDF81633; Tue, 6 Feb 2018 18:34:33 +0200 (EET) From: Peter De Schrijver To: , , , , , , , , , CC: Peter De Schrijver Subject: [PATCH v3 09/11] cpufreq: tegra124-cpufreq: extend to support Tegra210 Date: Tue, 6 Feb 2018 18:34:10 +0200 Message-ID: <1517934852-23255-10-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517934852-23255-1-git-send-email-pdeschrijver@nvidia.com> References: <1517934852-23255-1-git-send-email-pdeschrijver@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.21.24.170] X-ClientProxiedBy: UKMAIL101.nvidia.com (10.26.138.13) To UKMAIL101.nvidia.com (10.26.138.13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Tegra210 has a very similar CPU clocking scheme than Tegra124. So add support in this driver. Also allow for the case where the CPU voltage is controlled directly by the DFLL rather than by a separate regulator object. Signed-off-by: Peter De Schrijver --- drivers/cpufreq/tegra124-cpufreq.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/cpufreq/tegra124-cpufreq.c b/drivers/cpufreq/tegra124-cpufreq.c index 4353025..f8e01a8 100644 --- a/drivers/cpufreq/tegra124-cpufreq.c +++ b/drivers/cpufreq/tegra124-cpufreq.c @@ -64,7 +64,8 @@ static void tegra124_cpu_switch_to_pllx(struct tegra124_cpufreq_priv *priv) { clk_set_parent(priv->cpu_clk, priv->pllp_clk); clk_disable_unprepare(priv->dfll_clk); - regulator_sync_voltage(priv->vdd_cpu_reg); + if (priv->vdd_cpu_reg) + regulator_sync_voltage(priv->vdd_cpu_reg); clk_set_parent(priv->cpu_clk, priv->pllx_clk); } @@ -89,10 +90,10 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev) return -ENODEV; priv->vdd_cpu_reg = regulator_get(cpu_dev, "vdd-cpu"); - if (IS_ERR(priv->vdd_cpu_reg)) { - ret = PTR_ERR(priv->vdd_cpu_reg); - goto out_put_np; - } + if (IS_ERR(priv->vdd_cpu_reg) != -EPROBE_DEFER) + priv->vdd_cpu_reg = NULL; + else + return -EPROBE_DEFER; priv->cpu_clk = of_clk_get_by_name(np, "cpu_g"); if (IS_ERR(priv->cpu_clk)) { @@ -148,7 +149,6 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev) clk_put(priv->cpu_clk); out_put_vdd_cpu_reg: regulator_put(priv->vdd_cpu_reg); -out_put_np: of_node_put(np); return ret; @@ -181,7 +181,8 @@ static int __init tegra_cpufreq_init(void) int ret; struct platform_device *pdev; - if (!of_machine_is_compatible("nvidia,tegra124")) + if (!(of_machine_is_compatible("nvidia,tegra124") + || of_machine_is_compatible("nvidia,tegra210"))) return -ENODEV; /* -- 1.9.1