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[209.132.180.67]) by mx.google.com with ESMTP id 91-v6si1784174ply.413.2018.02.06.10.39.39; Tue, 06 Feb 2018 10:39:53 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@google.com header.s=20161025 header.b=Tt3l0+PZ; dkim=fail header.i=@chromium.org header.s=google header.b=bE6LI91I; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753200AbeBFShW (ORCPT + 99 others); Tue, 6 Feb 2018 13:37:22 -0500 Received: from mail-ua0-f193.google.com ([209.85.217.193]:42743 "EHLO mail-ua0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752755AbeBFShO (ORCPT ); Tue, 6 Feb 2018 13:37:14 -0500 Received: by mail-ua0-f193.google.com with SMTP id 47so1827513uau.9 for ; Tue, 06 Feb 2018 10:37:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=OGEcRIU1eqtovhPxtbYCY9K+LZaf/jA24X0msGbuPaA=; b=Tt3l0+PZmWJ2QYSp9qIn+ZjCXvCeREE3ZAwCr7vSoGywQ4rddm976XOAQUXlyWEzIG 3tCBsa4x8Gd22ssJYqWY4mbuVYOOuitad5jf3TNRaz+gVtHYCGhASz60+em3spMb9ZmC QZhv6aP/3LLS0LDT7uTzC1p4uf/2E1VFaRewxY5yCqgiObojpPlU1M5DjDWshCQsU96f aqu9u51MR7dkKvqL/OczEkvUFAHsXqPurOkPe0U3vvAnm3KAkPTo+7nnL1pvsO4oVc6T zJJs1Xtct2YGuO0LnKGcz5uxpscI9mUovyfff62JNQ4UsGpZwEtG7XuSKsYrVIHgFQcQ 9u0A== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=OGEcRIU1eqtovhPxtbYCY9K+LZaf/jA24X0msGbuPaA=; b=bE6LI91I/xS4G0wCEDnObYQf95v5p2r/y+GebHR0IahIaYPmHjAjpFAC4fKmvgfgso J2KUSiNZIkxuBE89UGUt4n2cevzoX1jjBsQgqUZvzRzw7LeFhwjkpfzVaiqa7eiM3gY3 SATTQF2RdDchED+20pT+PnOQ2xAdeauGEJRj0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:sender:in-reply-to:references:from :date:message-id:subject:to:cc; bh=OGEcRIU1eqtovhPxtbYCY9K+LZaf/jA24X0msGbuPaA=; b=XCJzLacTfWdq6VRUlNlIvM3JPPtdh6D9QbZHj21qml+0dsG2wFOnbWUQx/9yNqPO8s uRM0b5SjXqF17k8t9QhnsTDbNVoGW6O/suMwwO0JvChbQYcH2V5QY+QOF5wCOYWuA0OI 7Ej1xBErNYK0/h7xUOfjGTxUYJF7sa65u4Pgjdp031a+ZDzbdh3TqovyAXhqs7sg1rnG pLV63HPAtE70pWEQt+xDfGvyTKfQVTZJBSNAfH+qTnCAYzLBHJG/obdc+WntbQ19DxaR dqS3ZW/HJ1KGCfqsCBTXu4i/uxPbvFX6vmV7/o/IcYW3QOnqUWr3MeLNd0dSjU71UBVP kRwA== X-Gm-Message-State: APf1xPDn/gFEe9ePMhUGE2sCuHXjVCczIx3tjsKIZjtgVaQx2jTw88WX GPJU3hdLdrCDxztLGW+o1QR9lpoPiuZXRSUcNFRG3w== X-Received: by 10.176.112.181 with SMTP id q21mr3126107ual.105.1517942233132; Tue, 06 Feb 2018 10:37:13 -0800 (PST) MIME-Version: 1.0 Received: by 10.31.95.139 with HTTP; Tue, 6 Feb 2018 10:37:12 -0800 (PST) In-Reply-To: <20180126221808.GE28313@codeaurora.org> References: <20180125163216.29018-1-rnayak@codeaurora.org> <20180125163216.29018-3-rnayak@codeaurora.org> <20180126221808.GE28313@codeaurora.org> From: Doug Anderson Date: Tue, 6 Feb 2018 10:37:12 -0800 X-Google-Sender-Auth: QJFpQkdOZaqEUx5CLjJlyGPdGyM Message-ID: Subject: Re: [PATCH 2/2] arm64: dts: sdm845: Add serial console support To: Stephen Boyd Cc: Rajendra Nayak , Andy Gross , LKML , linux-arm-msm@vger.kernel.org, Linux ARM , devicetree@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Fri, Jan 26, 2018 at 2:18 PM, Stephen Boyd wrote: > On 01/25, Rajendra Nayak wrote: >> diff --git a/arch/arm64/boot/dts/qcom/sdm845-pins.dtsi b/arch/arm64/boot/dts/qcom/sdm845-pins.dtsi >> new file mode 100644 >> index 000000000000..b97f99e6f4b4 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/qcom/sdm845-pins.dtsi >> @@ -0,0 +1,32 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Copyright (c) 2018, The Linux Foundation. All rights reserved. >> + */ >> + >> +&tlmm { > > I'm not the maintainer, but I find this approach to the pins > really annoying. I have to flip to another file to figure out how > a board has configured the pins. And we may bring in a bunch of > settings that we don't ever use on some board too. Why can't we > put the settings in the board file directly? I'm not so familiar with how things work with Qualcomm, but in general I think putting this in the "board" file is a bad idea. I'd be OK with putting this directly in the SoC file (though it might get unwieldy?), but not moving things to the board file as was done with v2 of this patch. Said another way: nearly board that uses SDM845 that uses UART2 will have the same definitions for these pins so we shouldn't be duplicating it across every board, right? I'll also respond to the v2 patch so it's obvious there is feedback there... -Doug