Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Subject: Re: [PATCH v2 01/16] dt-bindings: clock: mediatek: add missing
 required #reset-cells
To:     sean.wang@mediatek.com, robh+dt@kernel.org, mark.rutland@arm.com,
        devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org
Cc:     linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        Rob Herring <robh@kernel.org>,
        Stephen Boyd <sboyd@codeaurora.org>
References: <cover.1517910489.git.sean.wang@mediatek.com>
 <d58fcf36319254d6de4c7fe100cbdca1bbec27a5.1517910489.git.sean.wang@mediatek.com>
From:   Matthias Brugger <matthias.bgg@gmail.com>
Message-ID: <391278e5-9b72-1142-0262-5d286fe17d8d@gmail.com>
Date:   Wed, 7 Feb 2018 11:45:38 +0100
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101
 Thunderbird/52.5.2
MIME-Version: 1.0
In-Reply-To: <d58fcf36319254d6de4c7fe100cbdca1bbec27a5.1517910489.git.sean.wang@mediatek.com>
Content-Type: text/plain; charset=utf-8
Content-Language: en-US
Content-Transfer-Encoding: 8bit
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk


On 02/06/2018 10:52 AM, sean.wang@mediatek.com wrote:
> From: Sean Wang <sean.wang@mediatek.com>
> 
> All ethsys, pciesys and ssusbsys internally include reset controller, so
> explicitly add back these missing cell definitions to related bindings
> and examples.
> 
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Stephen Boyd <sboyd@codeaurora.org>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
>  Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt   | 2 ++
>  Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt  | 2 ++
>  Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt | 2 ++
>  3 files changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
> index 7aa3fa1..8f5335b 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
> @@ -9,6 +9,7 @@ Required Properties:
>  	- "mediatek,mt2701-ethsys", "syscon"
>  	- "mediatek,mt7622-ethsys", "syscon"
>  - #clock-cells: Must be 1
> +- #reset-cells: Must be 1
>  
>  The ethsys controller uses the common clk binding from
>  Documentation/devicetree/bindings/clock/clock-bindings.txt
> @@ -20,4 +21,5 @@ ethsys: clock-controller@1b000000 {
>  	compatible = "mediatek,mt2701-ethsys", "syscon";
>  	reg = <0 0x1b000000 0 0x1000>;
>  	#clock-cells = <1>;
> +	#reset-cells = <1>;

The example is already fixed upstream, but I forgot the binding description,
please rebase this patch.

And please don't forget to add all clock maintainers.

Regards,
Matthias