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[209.132.180.67]) by mx.google.com with ESMTP id v8-v6si1051612plg.673.2018.02.07.05.08.40; Wed, 07 Feb 2018 05:08:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=pKdQWrD3; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753956AbeBGNHz (ORCPT + 99 others); Wed, 7 Feb 2018 08:07:55 -0500 Received: from fllnx209.ext.ti.com ([198.47.19.16]:19252 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753539AbeBGNHx (ORCPT ); Wed, 7 Feb 2018 08:07:53 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w17D6aZo026341; Wed, 7 Feb 2018 07:06:36 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1518008796; bh=JXfrg0y9ZHxmpMne1AgT6ZAXhJUwUXH90sASOAIiQ1s=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=pKdQWrD3/sEwwin8aGz3nIV7o7rNQgQorWQrXTenxaf0M8fUaNvb2P8cDUoOmYepE o/PsV1BWiWQB6JsJw/L9WPI+EkJGgytuQQnO3Vo8EEJW1MpxbJgi0hHcCItu8Rw8gi /GNd00eDxXkf61J2XlxxhC4gCdU+G0uF0rdy7/fw= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w17D6Zs0021810; Wed, 7 Feb 2018 07:06:36 -0600 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Wed, 7 Feb 2018 07:06:35 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Wed, 7 Feb 2018 07:06:35 -0600 Received: from [172.24.190.171] (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w17D6Vb1018978; Wed, 7 Feb 2018 07:06:32 -0600 Subject: Re: [PATCH] ARM: dts: da850-evm: add clock properties to the nand node To: Bartosz Golaszewski , David Lechner CC: Bartosz Golaszewski , Kevin Hilman , Rob Herring , Mark Rutland , Russell King , arm-soc , linux-devicetree , LKML References: <20180205155222.22189-1-brgl@bgdev.pl> <3f171f6a-bcea-65ec-d56d-f6ae24660f34@ti.com> <54dbdb98-e0e4-c8c9-fec4-2f050745d9be@ti.com> <794024f3-f87a-58ed-2722-a4a2d09df3ce@lechnology.com> <4aa2ab13-7890-6904-86b3-e2dbcb6d6daa@lechnology.com> From: Sekhar Nori Message-ID: <37e034fe-5951-9a58-8698-d34226e8279e@ti.com> Date: Wed, 7 Feb 2018 18:36:30 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wednesday 07 February 2018 12:15 AM, Bartosz Golaszewski wrote: > 2018-02-06 19:25 GMT+01:00 David Lechner : >> On 02/06/2018 12:16 PM, David Lechner wrote: >>> >>> On 02/06/2018 07:51 AM, Sekhar Nori wrote: >>>> >>>> On Tuesday 06 February 2018 06:38 PM, Bartosz Golaszewski wrote: >>>>> >>>>> 2018-02-06 12:07 GMT+01:00 Sekhar Nori : >>>>>> >>>>>> On Monday 05 February 2018 09:22 PM, Bartosz Golaszewski wrote: >>>>>>> >>>>>>> From: Bartosz Golaszewski >>>>>>> >>>>>>> Make nand work with the common clock framework by specifying which >>>>>>> clock should be used and what name to look up. >>>>>>> >>>>>>> Signed-off-by: Bartosz Golaszewski >>>>>>> --- >>>>>>> arch/arm/boot/dts/da850-evm.dts | 3 +++ >>>>>>> 1 file changed, 3 insertions(+) >>>>>>> >>>>>>> diff --git a/arch/arm/boot/dts/da850-evm.dts >>>>>>> b/arch/arm/boot/dts/da850-evm.dts >>>>>>> index a86a8a1816f2..2602ad8e99ee 100644 >>>>>>> --- a/arch/arm/boot/dts/da850-evm.dts >>>>>>> +++ b/arch/arm/boot/dts/da850-evm.dts >>>>>>> @@ -296,6 +296,9 @@ >>>>>>> reg = <0 0x02000000 0x02000000 >>>>>>> 1 0x00000000 0x00008000>; >>>>>>> >>>>>>> + clocks = <&psc0 3>; >>>>>>> + clock-names = "aemif"; >>>>>> >>>>>> >>>>>> Looks like this is being added only to satisfy the devm_clk_get() call >>>>>> in nand_davinci_probe() which I think is superfluous since we also >>>>>> enable the same clock in aemif_probe(). >>>>>> >>>>>> Perhaps the better solution is to drip the clk code in >>>>>> drivers/mtd/nand/davinci_nand.c and shift legacy code to start using >>>>>> drivers/memory/aemif.c as well? This way we can also drop >>>>>> arch/arm/mach-davinci/aemif.c >>>>>> >>>>>> Thanks, >>>>>> Sekhar >>>>> >>>>> >>>>> Yes, this sounds good, but I think we should leave it for later as an >>>>> additional improvement, once everything else is in place. I think >>>>> these patches should be applied together with David's series in order >>>>> to not break the support on davinci boards and the aemif work would go >>>>> in later as a follow-up. How about that? >>>> >>>> >>>> No, I dont think we should add temporary hacks to DT to work around >>>> driver issues (I do think its a hack since the clock belongs to aemif >>>> module not NAND flash). >>>> >>>> An easier driver hack might be to not treat devm_clk_get() failure in >>>> davinci_nand.c as catastrophic. It will safely fail in DT case and we >>>> should get the clock in legacy boot case. >>>> >>>> I think we are looking at a driver update dependency anyway. >>> >>> >>> It looks like keystone.dtsi is using the clock-ranges property in the >>> aemif node to pass the clock to child nodes. Could we not do the same >>> in da850.dtsi? >> >> >> Bartosz, please try this instead of your patch. >> >> FYI, this is just following the existing memory-controllers/ti-aemif.txt >> device tree bindings, so not a "hack". >> >> --- >> diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi >> index 3a1f2ce..ff9d807 100644 >> --- a/arch/arm/boot/dts/da850.dtsi >> +++ b/arch/arm/boot/dts/da850.dtsi >> @@ -796,6 +796,8 @@ >> ranges = <0 0 0x60000000 0x08000000 >> 1 0 0x68000000 0x00008000>; >> clocks = <&psc0 3>; >> + clock-names = "aemif"; >> + clock-ranges; >> status = "disabled"; >> }; >> memctrl: memory-controller@b0000000 { >> --- > > Yes, this works. Sekhar: can we include it in David's series, while > still keeping the plan to move legacy boards to using the aemif > driver? Okay. Fine with me. Actually the chipselect node already has clock-ranges defined, but that doesn't have any meaning unless its also included in aemif node. Thanks, Sekhar