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[209.132.180.67]) by mx.google.com with ESMTP id a33-v6si1257532pld.666.2018.02.07.08.03.02; Wed, 07 Feb 2018 08:03:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=QFI3LQAb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932091AbeBGQBI (ORCPT + 99 others); Wed, 7 Feb 2018 11:01:08 -0500 Received: from mail-wm0-f68.google.com ([74.125.82.68]:52797 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754138AbeBGQBG (ORCPT ); Wed, 7 Feb 2018 11:01:06 -0500 Received: by mail-wm0-f68.google.com with SMTP id g1so4069123wmg.2; Wed, 07 Feb 2018 08:01:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=qWJPmv+Up23q1NeHnTsOO3HvmHU3dDDV/BAZY7L/jk4=; b=QFI3LQAbSrQSUVNMWSRM/E0WVP9tnNdMUeQgSDwR4eYHB0kzavDyt6BSGaIJd3LNNw VnJ6zK4KQUkU7G1x9OzAxpl7xnqiV9L8NiWyP1/d6ugrYqlPnKrM6RxlqKPGfQAoy6rb QHfNkq1+UWcqr9xHHnDoitnultkvQ5e7doaTXXvgfjk69V8BD9Tv5t9NqhkdjjHnJMcT KXZ5Pu2kqSK7O5kbXb3xupoE0Dp1wi1Tc8dp/TcceghQXE2G8VOVP8rS3PUjhI8cvryF +cd2xjDKCX8lDQMZcgs6wTROPguqBm5xByhV4MGsiuzO2WcWLWelO/aNnGLVV/UNgKwb /bhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=qWJPmv+Up23q1NeHnTsOO3HvmHU3dDDV/BAZY7L/jk4=; b=tzMFWK0lXiLCpmc+hkXfUEi1PiM90WoReALFcVeHeWKYCdFmJhvcdlRpJpwE6uUlKp 9i8YTRxI3G0x3lX4S7ZRInDvgARrMExSziQyQGDEamv0wllyJDWkEvhki48T2Wwl6Yho BS6CNhlTjii4ygq1RmOQD/n/0KNUInc3O9RlFTcT6y3TH6nKy9ufuTN8zrLnec/k9ckv UPxdPVq5gESpRP6lkY4kK4Iv1Qp36U1DbRFRTgnOrwx7yjq1GFoBwDqcWegfDMMgwm5+ Mv4tztQD45HD/1apgSbse3WFAJ9sb+9+bTNbIepa6JMi64Uivj09dQaPTbI7KkimiySI Yq7g== X-Gm-Message-State: APf1xPB/ojcRvb01T427eb71sszcEfxuzBEN7Z5VnahNbJGE/D8sm7+o sYsPsl2IlvpQGjtb5OS2gzpAUBlX X-Received: by 10.28.122.12 with SMTP id v12mr4818275wmc.66.1518019263510; Wed, 07 Feb 2018 08:01:03 -0800 (PST) Received: from ziggy.stardust ([37.223.139.174]) by smtp.gmail.com with ESMTPSA id y64sm1716407wmg.35.2018.02.07.08.01.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Feb 2018 08:01:02 -0800 (PST) Subject: Re: [PATCH] arm: dts: mt7623: enable all four available UARTs on bananapi-r2 To: Sean Wang Cc: robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <1514043318.30687.10.camel@mtkswgap22> <1516697505.12197.30.camel@mtkswgap22> From: Matthias Brugger Message-ID: Date: Wed, 7 Feb 2018 17:01:01 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.2 MIME-Version: 1.0 In-Reply-To: <1516697505.12197.30.camel@mtkswgap22> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 01/23/2018 09:51 AM, Sean Wang wrote: > On Sat, 2017-12-23 at 23:35 +0800, Sean Wang wrote: >> On Sat, 2017-12-23 at 08:52 +0100, Matthias Brugger wrote: >>> >>> On 12/22/2017 07:06 AM, sean.wang@mediatek.com wrote: >>>> From: Sean Wang >>>> >>>> On bpi-r2 board, totally there're four uarts which we usually called >>>> uart[0-3] helpful to extend slow I/O devices. Among those ones, uart2 has >>>> dedicated pin slot which is used to conolse log. uart[0-1] appear at the >>>> 40-pins connector and uart3 has no pinout, but just has test points (TP47 >>>> for TX and TP48 for RX, respectively) nearby uart2. Also, some missing >>>> pinctrl is being complemented for those devices. >>>> >>>> Signed-off-by: Sean Wang >>>> --- >>>> arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 26 ++++++++++++++++++++++++-- >>>> 1 file changed, 24 insertions(+), 2 deletions(-) >>>> >>>> diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts >>>> index 7bf5aa2..64bf5db 100644 >>>> --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts >>>> +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts >>>> @@ -409,6 +409,20 @@ >>>> ; >>>> };do you like it or quite want me to remove the uart3 node? >>>> }; >>>> + >>>> + uart2_pins_a: uart@2 { >>>> + pins_dat { >>>> + pinmux = , >>>> + ; >>>> + }; >>>> + }; >>>> + >>>> + uart3_pins_a: uart@3 { >>>> + pins_dat { >>>> + pinmux = , >>>> + ; >>>> + }; >>>> + }; >>>> }; >>>> >>>> &pwm { >>>> @@ -454,16 +468,24 @@ >>>> &uart0 { >>>> pinctrl-names = "default"; >>>> pinctrl-0 = <&uart0_pins_a>; >>>> - status = "disabled"; >>>> + status = "okay"; >>>> }; >>>> >>>> &uart1 { >>>> pinctrl-names = "default"; >>>> pinctrl-0 = <&uart1_pins_a>; >>>> - status = "disabled"; >>>> + status = "okay"; >>>> }; >>>> >>>> &uart2 { >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&uart2_pins_a>; >>>> + status = "okay"; >>>> +}; >>>> + >>>> +&uart3 { >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&uart3_pins_a>; >>>> status = "okay"; >>>> }; >>>> >>> >>> Why do we want to enable uart3 when there are only test points? >>> It is not very useful, or do I oversee something? >>> > >> I have been listening to the sound from potential users of bpi-r2 to >> understand what assistance I have to provide to them. Something could >> be seen through [1] in the forum to know they had been trying hard to >> explore all available UARTs from the SoC in the last weeks. The patch >> should be really useful for these people and for the extra soldering >> it shouldn't become a problem for these makers. >> >> [1] http://forum.banana-pi.org/t/gpio-uart-not-the-debug-port/3748 >> >> Sean >> > > Hi, Matthias > > do you like it or quite want me to remove the uart3 node? > > I can take it into account along with other pending dts changes in my > queue. > Sorry for the late answer. Do I understand correctly that uart3 is routed to TP47 and TP48, and these test points are accessible through the SATA connector? Doesn't they break SATA then? I think as they are only available through a non-documented test point, we shouldn't enable it. Regards, Matthias