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[209.132.180.67]) by mx.google.com with ESMTP id b1-v6si1769039pld.281.2018.02.09.08.59.02; Fri, 09 Feb 2018 08:59:16 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=mqqTNSqc; dkim=pass header.i=@codeaurora.org header.s=default header.b=N8RpRc4t; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752246AbeBIQ5r (ORCPT + 99 others); Fri, 9 Feb 2018 11:57:47 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:34336 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752193AbeBIQ5p (ORCPT ); Fri, 9 Feb 2018 11:57:45 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id CB5BA60558; Fri, 9 Feb 2018 16:57:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1518195464; bh=1sUKz+/hekpDpfsLXvZDbZR0Vlm1XVngfNP6x4vSJNM=; h=From:To:Cc:Subject:Date:From; b=mqqTNSqcHetjjbnaJcnzR9kWkMe82AEfiq8yiLkfPQNyt/yzSV3MejA1Tid1hTHnK Ro58Qmw6uNaG22a5k/XGE6WnYHk3lrg8ta+XBXWysEBhPgbeZDRFQHCfNhG9YFusNT CaI7QQl5ewoIrSpEtOljrJK3hbs/Ep3DVUKIRzDk= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 41CBF60558; Fri, 9 Feb 2018 16:57:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1518195463; bh=1sUKz+/hekpDpfsLXvZDbZR0Vlm1XVngfNP6x4vSJNM=; h=From:To:Cc:Subject:Date:From; b=N8RpRc4tD7frWBW/Np0zIbMnrPZGYxylHBA45ehuLMolXH3Ti+mV6QgkE21Ygz+6L 7JE1NfSOD7PTan0HZ+A5Ejjrp4nT2R2gHukQPAQaQIc2reYwefo/rjtEY028l/1E+m gjlTUx1l3sBcYUYRSlmdKAM4phYgjmc/AgQ+a4cE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 41CBF60558 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, asathyak@codeaurora.org, Lina Iyer Subject: [PATCH v6 0/2] irqchip: qcom: add support for PDC interrupt controller Date: Fri, 9 Feb 2018 09:57:33 -0700 Message-Id: <20180209165735.19151-1-ilina@codeaurora.org> X-Mailer: git-send-email 2.15.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Changes since v5: - Fixed comment style of SPDX Changes since v4: - Code clean up as suggested by Marc On newer Qualcomm Techonologies Inc's SoCs like the SDM845, the GIC is in a power domain that can be powered off when not needed. Interrupts that need to be sensed even when the GIC is powered off, are routed through an interrupt controller in an always-on domain called the Power Domain Controller a.k.a PDC. This series adds support for the PDC's interrupt controller. Please consider reviewing these patches. RFC v1: https://patchwork.kernel.org/patch/10180857/ RFC v2: https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1600634.html v3: https://lkml.org/lkml/2018/2/6/595 v4: https://www.spinics.net/lists/linux-arm-msm/msg32906.html Lina Iyer (2): drivers: irqchip: pdc: Add PDC interrupt controller for QCOM SoCs dt-bindings/interrupt-controller: pdc: descibe PDC device binding .../bindings/interrupt-controller/qcom,pdc.txt | 78 +++++ drivers/irqchip/Kconfig | 9 + drivers/irqchip/Makefile | 1 + drivers/irqchip/qcom-pdc.c | 314 +++++++++++++++++++++ 4 files changed, 402 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt create mode 100644 drivers/irqchip/qcom-pdc.c -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project