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[209.132.180.67]) by mx.google.com with ESMTP id i8-v6si1744plr.97.2018.02.09.11.55.49; Fri, 09 Feb 2018 11:56:08 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=T450Ypou; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752497AbeBITzN (ORCPT + 99 others); Fri, 9 Feb 2018 14:55:13 -0500 Received: from mail-io0-f180.google.com ([209.85.223.180]:39614 "EHLO mail-io0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750832AbeBITzL (ORCPT ); Fri, 9 Feb 2018 14:55:11 -0500 Received: by mail-io0-f180.google.com with SMTP id b198so10901467iof.6 for ; Fri, 09 Feb 2018 11:55:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=EFlLQ2p3OSXgAgYao0PBlpZ/kGPxVDFi6tK8egPI5eg=; b=T450Ypou9CgWtCOw+iU2xQ0yrJvnHwjgwpbN3LwCypLxRr0Oz9NiPhVQX5T06spgTL hK29zETMU/cXRrXPlhloCEKaJdXF68VZqFEi7hc0N8MZ7iCs8wqoEAB/tnhX2JnBDPoz 2piPW2lmFG7uaUm2cPYHqYhPZLuQPYhI2uaEFiymuxa8UeNERDSSty1sB0HOpt8md+9w gtQYmv5UiA5cRKSuH3B6Ih9ICFXauZx1Lt5h6hHpPiI3BnAOvI11CTssBt99EynFckCZ 64Tl5BxVN4aotUNomH2FpnR/mti+8EqYKtV6zvTNKmkNrTFRWWcP5lJXXQOZxFPBipKd STxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:sender:in-reply-to:references:from :date:message-id:subject:to:cc; bh=EFlLQ2p3OSXgAgYao0PBlpZ/kGPxVDFi6tK8egPI5eg=; b=sWpctNhcAKJhR6b7J3okpzAuli/c9wkqcXHFV/oMxKq842EiFY1ppGU2IuHzA8LtCl uZxqsHm0xMfOj7WyJfhy95g4YMM9FT+NOh6yfpPdNhI26k24MCall+DFJbOh2E4JmkEf 0Wh0Z/KpGWzjAeK6FBVPcep9o92h0JJKo7/HPnK/EK5Hq9/vCDJJJ8slw85GppXl/G+Y JcJMxIBmYlJsMO4aQDst9tKhkHJMDfrJ9yHhFreqmIGekInOT008HSfGsozH308uX57/ ZRgpuriY5zqSC+G1T7SjIkhqeK2SmrWeZPsrR8G4WzuFxt8MOUPUfe047CcsXbptpLXk nIeg== X-Gm-Message-State: APf1xPDCf4LD0iHKenRjroLKpq7mz4xHn0XseWaNN8zL8WWWDBYwIjFb hsUNmf4kQ0AO/4Th5bK7uA2DeFIMtpxyFOtPxqY= X-Received: by 10.107.81.20 with SMTP id f20mr4547221iob.174.1518205739868; Fri, 09 Feb 2018 11:48:59 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.59.196 with HTTP; Fri, 9 Feb 2018 11:48:59 -0800 (PST) In-Reply-To: <20180209192515.qvvixkn5rz77oz6l@suse.de> References: <1518168340-9392-1-git-send-email-joro@8bytes.org> <1518168340-9392-10-git-send-email-joro@8bytes.org> <20180209190226.lqh6twf7thfg52cq@suse.de> <20180209192515.qvvixkn5rz77oz6l@suse.de> From: Linus Torvalds Date: Fri, 9 Feb 2018 11:48:59 -0800 X-Google-Sender-Auth: bACYifX2rINesSfjpji2yhbwHxk Message-ID: Subject: Re: [PATCH 09/31] x86/entry/32: Leave the kernel via trampoline stack To: Joerg Roedel Cc: Joerg Roedel , Thomas Gleixner , Ingo Molnar , "H . Peter Anvin" , "the arch/x86 maintainers" , Linux Kernel Mailing List , linux-mm , Andy Lutomirski , Dave Hansen , Josh Poimboeuf , Juergen Gross , Peter Zijlstra , Borislav Petkov , Jiri Kosina , Boris Ostrovsky , Brian Gerst , David Laight , Denys Vlasenko , Eduardo Valentin , Greg KH , Will Deacon , "Liguori, Anthony" , Daniel Gruss , Hugh Dickins , Kees Cook , Andrea Arcangeli , Waiman Long , Pavel Machek Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Feb 9, 2018 at 11:25 AM, Joerg Roedel wrote: > > Ugh, okay. So I switch to movsl, that should at least perform on-par > with the chain of 'pushl' instructions I had before. It should generally be roughly in the same ballpark. I think the instruction scheduling ends up basically breaking around microcoded instructions, which is why you'll get something like 12+n cycles for "rep movs" on some uarchs, but at that point it's probably mostly in the noise compared to all the other nasty PTI things. You won't see any of the _real_ advantages (which are about moving cachelines at a time), so with smallish copies you really only see the downsides of "rep movs", which is mainly that instruction scheduling hickup with any miocrocode. But with the iret and the cr3 movement, you aren't going to have a nice well-behaved pipeline anyway. Linus