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[209.132.180.67]) by mx.google.com with ESMTP id n185si528908pga.142.2018.02.09.18.18.33; Fri, 09 Feb 2018 18:19:12 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@oracle.com header.s=corp-2017-10-26 header.b=i7B1zrzS; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=oracle.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751317AbeBJCQ6 (ORCPT + 99 others); Fri, 9 Feb 2018 21:16:58 -0500 Received: from userp2130.oracle.com ([156.151.31.86]:36658 "EHLO userp2130.oracle.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751122AbeBJCQ5 (ORCPT ); Fri, 9 Feb 2018 21:16:57 -0500 Received: from pps.filterd (userp2130.oracle.com [127.0.0.1]) by userp2130.oracle.com (8.16.0.22/8.16.0.22) with SMTP id w1A2Gf3g062779; Sat, 10 Feb 2018 02:16:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=mime-version : message-id : date : from : to : cc : subject : content-type : content-transfer-encoding; s=corp-2017-10-26; bh=woXj/Smq63dejTyeKun+TWJlcy+KjyOvya3LdOy5tWw=; b=i7B1zrzSrWG3oU8yNBU8V+R/m+vzkR4kFuTQvOC/qB9Vu3qrruVD8BaxsZ5V3JT5IH6D i38qAN6FsM3qJZ1gi+DhWCqjNWVx1vgHesPMsSVKHaRazekfcvNX7s6YjfACMIGgixM4 n1q4yoMkx3ND8qDU8KCjXPy3GZqKScGlWLes2bXy3cK9UI6vwHUVscnVzjyp2knMCT0W WbSZjfMRECZi0VgsHVwClIMLAsZl600k2UhQZbu0G4tSF6o3A97jxpdSzCgCEaXoxtj2 cO2b3nmG061ERyLNTuHnTIEUO/czH+2vU/MZjLsgxkBwm77PpbxtJLRGkvE6fa1Vfswb uw== Received: from aserv0022.oracle.com (aserv0022.oracle.com [141.146.126.234]) by userp2130.oracle.com with ESMTP id 2g1papr5b2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sat, 10 Feb 2018 02:16:41 +0000 Received: from userv0122.oracle.com (userv0122.oracle.com [156.151.31.75]) by aserv0022.oracle.com (8.14.4/8.14.4) with ESMTP id w1A2Ge8G016569 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 10 Feb 2018 02:16:40 GMT Received: from abhmp0015.oracle.com (abhmp0015.oracle.com [141.146.116.21]) by userv0122.oracle.com (8.14.4/8.14.4) with ESMTP id w1A2Gdg8030582; Sat, 10 Feb 2018 02:16:39 GMT MIME-Version: 1.0 Message-ID: <3b565dd4-0b90-4301-b918-aba529d54a81@default> Date: Fri, 9 Feb 2018 18:16:39 -0800 (PST) From: Liran Alon To: Cc: , , , , , , , Subject: Re: [PATCH] x86/kvm/vmx: Don't halt vcpu when L1 is injecting events to L2 X-Mailer: Zimbra on Oracle Beehive Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-Proofpoint-Virus-Version: vendor=nai engine=5900 definitions=8800 signatures=668666 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=1 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1711220000 definitions=main-1802100026 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ----- pbonzini@redhat.com wrote: > On 08/02/2018 13:09, Liran Alon wrote: > > ----- pbonzini@redhat.com wrote: > >> On 08/02/2018 06:13, Chao Gao wrote: > >=20 > > A possible patch to fix this is to change vmx_hwapic_irr_update() > such that > > if is_guest_mode(vcpu)=3D=3Dtrue, we should return max(max_irr, rvi) an= d > return > > that value into apic_has_interrupt_for_ppr(). > > Need to verify that it doesn't break other flows but I think it > makes sense. > > What do you think? >=20 > Yeah, I think it makes sense though I'd need to look a lot more at > arch/x86/kvm/lapic.c and arch/x86/kvm/vmx.c to turn that into a > patch! >=20 > Paolo After thinking about this a bit more, I don't like my previous suggestion. As we don't semantically want to change the value returned from kvm_apic_ha= s_interrupt(). Instead, it makes more sense to change kvm_cpu_has_interrupt() to check for= RVI>PPR in case is_guest_mode(vcpu)=3D=3Dtrue. Something like (partial theoretical patch): @@ -97,6 +97,14 @@ int kvm_cpu_has_interrupt(struct kvm_vcpu *v) if (kvm_cpu_has_extint(v)) return 1; =20 + /* + * When running L2, L1 controls vmcs02 RVI via vmcs12. + * Therefore, it is possible RVI indicates pending interrupt + * for vCPU while LAPIC IRR is empty. + */ + if (is_guest_mode(v) && + (kvm_x86_ops->hwapic_has_interrupt(v) !=3D -1)) + return 1; + return kvm_apic_has_interrupt(v) !=3D -1; /* LAPIC */ } Where: +static int vmx_get_rvi(void) +{ + return ((u8)vmcs_read16(GUEST_INTR_STATUS) & 0xff); +} +static int vmx_hwapic_has_interrupt(struct kvm_vcpu *vcpu) +{ + int vector =3D vmx_get_rvi(vcpu); + return kvm_apic_has_interrupt_for_vector(vector); +} +int kvm_apic_has_interrupt_for_vector(struct kvm_vcpu *vcpu, int vector) +{ + struct kvm_lapic *apic =3D vcpu->arch.apic; + u32 ppr; + + if (!apic_enabled(apic)) + return -1; + + __apic_update_ppr(apic, &ppr); + return (((vector & 0xF0) > ppr) ? (vector) : (-1)); +} +EXPORT_SYMBOL_GPL(kvm_apic_has_interrupt_for_vector); Regards, -Liran