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[209.132.180.67]) by mx.google.com with ESMTP id 1-v6si10169pll.459.2018.02.09.18.43.32; Fri, 09 Feb 2018 18:43:45 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=B2gQiS2q; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752201AbeBJCm1 (ORCPT + 99 others); Fri, 9 Feb 2018 21:42:27 -0500 Received: from mail-pg0-f65.google.com ([74.125.83.65]:37974 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752058AbeBJCmX (ORCPT ); Fri, 9 Feb 2018 21:42:23 -0500 Received: by mail-pg0-f65.google.com with SMTP id l18so4856522pgc.5 for ; Fri, 09 Feb 2018 18:42:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=v/v+3HombVK7nJTKFPm90AlgwBxtDhnbGCrwGuOsoZk=; b=B2gQiS2qBNI0c80tBZ7YE8/K4abro8PAizwAUSy4ZIxx3FkeaG0YFCBjKSrrlkaJNT +wAncFNBp81+n++5XIh4B++1kUHqYrBgkgDSxpNrq3ibmMwug3LvyhMdcNSHiA5X2ngj o4RK1SK60Nf4W47bZUIYw930Uz5fBiXI1GOmk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=v/v+3HombVK7nJTKFPm90AlgwBxtDhnbGCrwGuOsoZk=; b=bU8VGzdUyXkurtUE+9OOqlla2uQhetQ+gF4BF9JVxVasgYkX9L1SJ0g6bjKG3AOD7j vOO/p2zDErnQ4Mdg9ekBSozhvmwXOTYvG0wHZ/UGhER5WkA2zA3uh53ksQGBGTJTlDiK 61qEK/3L+uTyg1L9zmLRh6Pk2CMCjWJMGeupDR+dQvGMb+JMrWboSi5wJqTquetn+eda njKO0seQKc8b62QYrnF2YledmIvF69Lwh6kDDhHWj+WV/QkpXjD4jXutkwUTKwvIkoAk D0KL+CnEyOC74DjW8syoY9CoaVtzvH7LkvY4KpILs++YA9eIsaxm7ipThg9Ks9PI6U0I wCRA== X-Gm-Message-State: APf1xPACkQ6ORxBBzz83CYhomHNRUWXwv8wM/iyU7/s3RiNNU8A/h+gM TwAbMohKtZ+FIr9ZMgq/Z5ZW X-Received: by 10.99.183.68 with SMTP id w4mr3988915pgt.221.1518230542857; Fri, 09 Feb 2018 18:42:22 -0800 (PST) Received: from localhost.localdomain ([2405:204:7185:1f8f:fdb9:648e:14d3:8b97]) by smtp.gmail.com with ESMTPSA id z6sm7883286pgu.49.2018.02.09.18.42.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Feb 2018 18:42:22 -0800 (PST) From: Manivannan Sadhasivam To: mturquette@baylibre.com, sboyd@codeaurora.org, afaerber@suse.de, robh+dt@kernel.org, mark.rutland@arm.com Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, davem@davemloft.net, mchehab@kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, viresh.kumar@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 04/11] clk: actions: Add common clock driver support Date: Sat, 10 Feb 2018 08:11:13 +0530 Message-Id: <20180210024120.27503-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180210024120.27503-1-manivannan.sadhasivam@linaro.org> References: <20180210024120.27503-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for Actions Semi common clock driver with generic structures and interface functions. Signed-off-by: Manivannan Sadhasivam --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/actions/Kconfig | 4 ++ drivers/clk/actions/Makefile | 3 ++ drivers/clk/actions/owl-common.c | 84 ++++++++++++++++++++++++++++++++++++++++ drivers/clk/actions/owl-common.h | 40 +++++++++++++++++++ 6 files changed, 133 insertions(+) create mode 100644 drivers/clk/actions/Kconfig create mode 100644 drivers/clk/actions/Makefile create mode 100644 drivers/clk/actions/owl-common.c create mode 100644 drivers/clk/actions/owl-common.h diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 98ce9fc6e6c0..6313a4f4327a 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -238,6 +238,7 @@ config COMMON_CLK_VC5 This driver supports the IDT VersaClock 5 and VersaClock 6 programmable clock generators. +source "drivers/clk/actions/Kconfig" source "drivers/clk/bcm/Kconfig" source "drivers/clk/hisilicon/Kconfig" source "drivers/clk/imgtec/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 71ec41e6364f..554b67e4d0c6 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o # please keep this section sorted lexicographically by directory path name +obj-$(CONFIG_ARCH_ACTIONS) += actions/ obj-$(CONFIG_COMMON_CLK_AT91) += at91/ obj-$(CONFIG_ARCH_ARTPEC) += axis/ obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/ diff --git a/drivers/clk/actions/Kconfig b/drivers/clk/actions/Kconfig new file mode 100644 index 000000000000..13a3e5083d43 --- /dev/null +++ b/drivers/clk/actions/Kconfig @@ -0,0 +1,4 @@ +config CLK_ACTIONS + bool "Clock driver for Actions Semi SoCs" + depends on ARCH_ACTIONS || COMPILE_TEST + default ARCH_ACTIONS diff --git a/drivers/clk/actions/Makefile b/drivers/clk/actions/Makefile new file mode 100644 index 000000000000..64a50fc2d335 --- /dev/null +++ b/drivers/clk/actions/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_CLK_ACTIONS) += clk-owl.o + +clk-owl-y += owl-common.o diff --git a/drivers/clk/actions/owl-common.c b/drivers/clk/actions/owl-common.c new file mode 100644 index 000000000000..a7cb698fdc86 --- /dev/null +++ b/drivers/clk/actions/owl-common.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// OWL common clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#include +#include +#include + +#include "owl-common.h" + +static const struct regmap_config owl_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xffff, + .fast_io = true, +}; + +static void owl_clk_set_regmap(const struct owl_clk_desc *desc, + struct regmap *regmap) +{ + int i; + struct owl_clk_common *clks; + + for (i = 0; i < desc->num_clks; i++) { + clks = desc->clks[i]; + if (!clks) + continue; + + clks->regmap = regmap; + } +} + +int owl_clk_regmap_init(struct platform_device *pdev, + const struct owl_clk_desc *desc) +{ + void __iomem *base; + struct device_node *node = pdev->dev.of_node; + struct regmap *regmap; + + base = of_iomap(node, 0); + regmap = devm_regmap_init_mmio(&pdev->dev, base, &owl_regmap_config); + if (IS_ERR_OR_NULL(regmap)) { + pr_err("failed to init regmap\n"); + return PTR_ERR(regmap); + } + + owl_clk_set_regmap(desc, regmap); + + return 0; +} + +int owl_clk_probe(struct device *dev, struct clk_hw_onecell_data *hw_clks) +{ + int i, ret; + struct clk_hw *hw; + + for (i = 0; i < hw_clks->num; i++) { + + hw = hw_clks->hws[i]; + + if (!hw) + continue; + + ret = devm_clk_hw_register(dev, hw); + if (ret) { + dev_err(dev, "Couldn't register clock %d - %s\n", + i, hw->init->name); + return ret; + } + } + + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_clks); + if (ret) + dev_err(dev, "Failed to add clock provider\n"); + + return ret; +} diff --git a/drivers/clk/actions/owl-common.h b/drivers/clk/actions/owl-common.h new file mode 100644 index 000000000000..e7ea23a6c8f1 --- /dev/null +++ b/drivers/clk/actions/owl-common.h @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// OWL common clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#ifndef _OWL_COMMON_H_ +#define _OWL_COMMON_H_ + +#include +#include + +struct device_node; + +struct owl_clk_common { + struct regmap *regmap; + struct clk_hw hw; +}; + +struct owl_clk_desc { + struct owl_clk_common **clks; + unsigned long num_clks; + struct clk_hw_onecell_data *hw_clks; +}; + +static inline struct owl_clk_common * + hw_to_owl_clk_common(const struct clk_hw *hw) +{ + return container_of(hw, struct owl_clk_common, hw); +} + +int owl_clk_regmap_init(struct platform_device *pdev, + const struct owl_clk_desc *desc); +int owl_clk_probe(struct device *dev, struct clk_hw_onecell_data *hw_clks); + +#endif /* _OWL_COMMON_H_ */ -- 2.14.1