Received: by 10.223.176.5 with SMTP id f5csp1377563wra; Fri, 9 Feb 2018 18:44:28 -0800 (PST) X-Google-Smtp-Source: AH8x227oGuf6xWUWSs3Kd3YaNAKAsnYgyEDyrKtj86iuqNB99rld+ubQ/38SZuqoZ+LSiiug+Ff4 X-Received: by 10.98.92.1 with SMTP id q1mr4780485pfb.238.1518230668803; Fri, 09 Feb 2018 18:44:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518230668; cv=none; d=google.com; s=arc-20160816; b=t+8iPzEuORTcMQp7FO5y4rDyG6vPyZ5cbMOghmSbhgzOIAQ/sDexYpEhaYe9/4Ofm5 CrU8eOAL3DG/+04JXHzCMn7ftP/69cv5O63uzrJzUBlpVxU3HxSejGtiXUa8Wp1aS3yq OqMIQ2i2Yr0cyYNWxoG5dOFtd7m8aE8TMFCfJhQWNW+noXtyomGthr7i9Dduxs6KQoL6 +z0DrKlf0mNYZjZUVHky9KroPrHGfntgnxXnsiKZdO4NsjmGT+9bWacv4rmbyfbUOzFe 8tatminFWM+jFdDsJBLgB91Sg2qB/TPb7UqFZas9CPIKkgI0Zy6Uy6nYnfIzPdQE/lIh n+5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=seVTnliGJc5xELZw9oAHHFfw1Sv3N8ggokUwzyYYyCM=; b=wjKKKEyPS71qjHZMGx38jJkCUWNpaZPMcVffdnX+rrxAij4p5/c+sIFDDYgujUtmH2 fzQRutEubCuP84s5s0x0Uk33Q54wA75IZ/TIsn9CoT8KoTxYojq5y423/wCle3STaneq cw0sK2h8S4vTj54YVU1TqUVFf82vH9exRlyfQ7chcXPQlvckV+8YTiHUF86LdS+e8NP1 Hed49AmGD3TjfWc8ypyOfDGYCi1gej5kZXfS0gLySciZA3gWQQZVLiUPPBTjCnFG49Ra KDF79MIg/8tWiplPCtjG6q+X+Gzbs4Ktkezc5nvtXh1WqG55OQe19OMNILgfUVRbUpgE X3QA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=So5ibdco; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e3si2183097pga.1.2018.02.09.18.44.14; Fri, 09 Feb 2018 18:44:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=So5ibdco; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752337AbeBJCmm (ORCPT + 99 others); Fri, 9 Feb 2018 21:42:42 -0500 Received: from mail-pl0-f66.google.com ([209.85.160.66]:38414 "EHLO mail-pl0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752305AbeBJCmj (ORCPT ); Fri, 9 Feb 2018 21:42:39 -0500 Received: by mail-pl0-f66.google.com with SMTP id 13so2328876plb.5 for ; Fri, 09 Feb 2018 18:42:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=seVTnliGJc5xELZw9oAHHFfw1Sv3N8ggokUwzyYYyCM=; b=So5ibdcoP3rVDklED3SJyaSw9e7pyBEKEm6aqwzMNWzqjp46TAMW4sgLZZ8p1HgGVd 1XC3wR6GWrusEtmvzZennpoQxbZj4jJTnK7EHetm9hcvBnuMVSDXq9I+g5/LeltpvFuj xGXYzn+ILDwSQ1ZP+17GESAQ9fnVTHfO6qfwo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=seVTnliGJc5xELZw9oAHHFfw1Sv3N8ggokUwzyYYyCM=; b=o+6oWvAHLlYOuBs+lc5XVSnaagdOZU+h0rI9JeVnTvf5sw7+SIJRUt5AH9PpuTFjxV Z0wK6m75h6lnYykNfLTrqg65Pshk3Oa4oB9lvlKGoYR11hFrzvXd3TRAHvHThr7az84t VP6T/BqykV8TEl6bRPsVHNldr+gtLlouEmUG6hN818pV1paIejFxVIz69IiJBzMqvPGU IjIZJ1UdvQG8BfyWV9aXAB9SODHSWjW3GbpIBYQfPJlN4+HqdBbjMbemVGXQYdkcFQam mo22i2q8ym1KxiEiVx1feUjQbTxN7GgxEUjl+vxsxWCw5u1uwyM/Av/d/BIe5Y5y3q9q 9RAg== X-Gm-Message-State: APf1xPBjgLSfbOX+BMeC9jmmXdYGHJcN5sqmkaPlR7dZIrnsoY2uDO44 xpLZoMmVbTB1hFbiXpfNDhGH X-Received: by 2002:a17:902:d83:: with SMTP id 3-v6mr4390406plv.82.1518230558375; Fri, 09 Feb 2018 18:42:38 -0800 (PST) Received: from localhost.localdomain ([2405:204:7185:1f8f:fdb9:648e:14d3:8b97]) by smtp.gmail.com with ESMTPSA id z6sm7883286pgu.49.2018.02.09.18.42.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Feb 2018 18:42:37 -0800 (PST) From: Manivannan Sadhasivam To: mturquette@baylibre.com, sboyd@codeaurora.org, afaerber@suse.de, robh+dt@kernel.org, mark.rutland@arm.com Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, davem@davemloft.net, mchehab@kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, viresh.kumar@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 06/11] clk: actions: Add mux clock support Date: Sat, 10 Feb 2018 08:11:15 +0530 Message-Id: <20180210024120.27503-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180210024120.27503-1-manivannan.sadhasivam@linaro.org> References: <20180210024120.27503-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for Actions Semi mux clock together with helper functions to be used in composite clock. Signed-off-by: Manivannan Sadhasivam --- drivers/clk/actions/Makefile | 1 + drivers/clk/actions/owl-mux.c | 60 ++++++++++++++++++++++++++++++++++++++++++ drivers/clk/actions/owl-mux.h | 61 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 122 insertions(+) create mode 100644 drivers/clk/actions/owl-mux.c create mode 100644 drivers/clk/actions/owl-mux.h diff --git a/drivers/clk/actions/Makefile b/drivers/clk/actions/Makefile index 1f0917872c9d..2d4aa8f35d90 100644 --- a/drivers/clk/actions/Makefile +++ b/drivers/clk/actions/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_CLK_ACTIONS) += clk-owl.o clk-owl-y += owl-common.o clk-owl-y += owl-gate.o +clk-owl-y += owl-mux.o diff --git a/drivers/clk/actions/owl-mux.c b/drivers/clk/actions/owl-mux.c new file mode 100644 index 000000000000..f9c6cf2540e4 --- /dev/null +++ b/drivers/clk/actions/owl-mux.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// OWL mux clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#include +#include + +#include "owl-mux.h" + +u8 owl_mux_helper_get_parent(const struct owl_clk_common *common, + const struct owl_mux_hw *mux_hw) +{ + u32 reg; + u8 parent; + + regmap_read(common->regmap, mux_hw->reg, ®); + parent = reg >> mux_hw->shift; + parent &= BIT(mux_hw->width) - 1; + + return parent; +} + +static u8 owl_mux_get_parent(struct clk_hw *hw) +{ + struct owl_mux *mux = hw_to_owl_mux(hw); + + return owl_mux_helper_get_parent(&mux->common, &mux->mux_hw); +} + +int owl_mux_helper_set_parent(const struct owl_clk_common *common, + struct owl_mux_hw *mux_hw, u8 index) +{ + u32 reg; + + regmap_read(common->regmap, mux_hw->reg, ®); + reg &= ~GENMASK(mux_hw->width + mux_hw->shift - 1, mux_hw->shift); + regmap_write(common->regmap, mux_hw->reg, + reg | (index << mux_hw->shift)); + + return 0; +} + +static int owl_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct owl_mux *mux = hw_to_owl_mux(hw); + + return owl_mux_helper_set_parent(&mux->common, &mux->mux_hw, index); +} + +const struct clk_ops owl_mux_ops = { + .get_parent = owl_mux_get_parent, + .set_parent = owl_mux_set_parent, + .determine_rate = __clk_mux_determine_rate, +}; diff --git a/drivers/clk/actions/owl-mux.h b/drivers/clk/actions/owl-mux.h new file mode 100644 index 000000000000..834284c8c3ae --- /dev/null +++ b/drivers/clk/actions/owl-mux.h @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// OWL mux clock driver +// +// Copyright (c) 2014 Actions Semi Inc. +// Author: David Liu +// +// Copyright (c) 2018 Linaro Ltd. +// Author: Manivannan Sadhasivam + +#ifndef _OWL_MUX_H_ +#define _OWL_MUX_H_ + +#include "owl-common.h" + +struct owl_mux_hw { + u32 reg; + u8 shift; + u8 width; +}; + +struct owl_mux { + struct owl_mux_hw mux_hw; + struct owl_clk_common common; +}; + +#define OWL_MUX_HW(_reg, _shift, _width) \ + { \ + .reg = _reg, \ + .shift = _shift, \ + .width = _width, \ + } + +#define OWL_MUX(_struct, _name, _parents, _reg, \ + _shift, _width, _flags) \ + struct owl_mux _struct = { \ + .mux_hw = OWL_MUX_HW(_reg, _shift, _width), \ + .common = { \ + .regmap = NULL, \ + .hw.init = CLK_HW_INIT_PARENTS(_name, \ + _parents, \ + &owl_mux_ops, \ + _flags), \ + }, \ + } + +static inline struct owl_mux *hw_to_owl_mux(const struct clk_hw *hw) +{ + struct owl_clk_common *common = hw_to_owl_clk_common(hw); + + return container_of(common, struct owl_mux, common); +} + +u8 owl_mux_helper_get_parent(const struct owl_clk_common *common, + const struct owl_mux_hw *mux_hw); +int owl_mux_helper_set_parent(const struct owl_clk_common *common, + struct owl_mux_hw *mux_hw, u8 index); + +extern const struct clk_ops owl_mux_ops; + +#endif /* _OWL_MUX_H_ */ -- 2.14.1