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[209.132.180.67]) by mx.google.com with ESMTP id h131si1571306pfc.222.2018.02.10.15.42.04; Sat, 10 Feb 2018 15:42:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@amazon.co.uk header.s=amazon201209 header.b=EUZN7bqz; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amazon.co.uk Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752956AbeBJXjt (ORCPT + 99 others); Sat, 10 Feb 2018 18:39:49 -0500 Received: from smtp-fw-9101.amazon.com ([207.171.184.25]:12571 "EHLO smtp-fw-9101.amazon.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752879AbeBJXjr (ORCPT ); Sat, 10 Feb 2018 18:39:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.co.uk; i=@amazon.co.uk; q=dns/txt; s=amazon201209; t=1518305987; x=1549841987; h=from:to:subject:date:message-id:mime-version: content-transfer-encoding; bh=NX/x5YA3PI3OixVq/2yYI7tT2Hy8cbOZGjCi9M9RRL8=; b=EUZN7bqzN2TaQ3a+rm0nHGc73/BlRtAfgwMp8xoX7Fx5Psi7KWvBgbFL EYbvGZrl+jj/sGQGpQH06y9mrCMQ1Tq33p1XaWO7tR4pnh5RaIN73/oPJ eHr/gOQlap73S7gXedLj3uBQb/MRWsNRZsUI34QtkQRBoVkXquIxp9II9 s=; X-IronPort-AV: E=Sophos;i="5.46,492,1511827200"; d="scan'208";a="722034694" Received: from sea3-co-svc-lb6-vlan3.sea.amazon.com (HELO email-inbound-relay-2a-1c1b5cdd.us-west-2.amazon.com) ([10.47.22.38]) by smtp-border-fw-out-9101.sea19.amazon.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 10 Feb 2018 23:39:44 +0000 Received: from uc8d3ff76b9bc5848a9cc.ant.amazon.com (pdx2-ws-svc-lb17-vlan3.amazon.com [10.247.140.70]) by email-inbound-relay-2a-1c1b5cdd.us-west-2.amazon.com (8.14.7/8.14.7) with ESMTP id w1ANdc7H126978 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Sat, 10 Feb 2018 23:39:40 GMT Received: from uc8d3ff76b9bc5848a9cc.ant.amazon.com (localhost [127.0.0.1]) by uc8d3ff76b9bc5848a9cc.ant.amazon.com (8.15.2/8.15.2/Debian-3) with ESMTP id w1ANdbK8031577; Sat, 10 Feb 2018 23:39:37 GMT Received: (from dwmw@localhost) by uc8d3ff76b9bc5848a9cc.ant.amazon.com (8.15.2/8.15.2/Submit) id w1ANdaSZ031574; Sat, 10 Feb 2018 23:39:36 GMT From: David Woodhouse To: tglx@linutronix.de, karahmed@amazon.de, sironi@amazon.de, x86@kernel.org, kvm@vger.kernel.org, torvalds@linux-foundation.org, pbonzini@redhat.com, linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, jmattson@google.com, rkrcmar@redhat.com, arjan.van.de.ven@intel.com, dave.hansen@intel.com Subject: [PATCH v2 0/6] Spectre v2 updates Date: Sat, 10 Feb 2018 23:39:21 +0000 Message-Id: <1518305967-31356-1-git-send-email-dwmw@amazon.co.uk> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Using retpoline ensures the kernel is safe because it doesn't contain any indirect branches, but firmware still can — and we make calls into firmware at runtime. Where the IBRS microcode support is available, use that before calling into firmware. While doing that, I noticed that we were calling C functions without telling the compiler about the call-clobbered registers. Stop that. This also contains the always_inline fix for the performance problem introduced by retpoline in KVM code, and fixes some other issues with the per-vCPU KVM handling for the SPEC_CTRL MSR. Finally, update the microcode blacklist to reflect the latest information from Intel. v2: Drop IBRS_ALL patch for the time being Add KVM MSR fixes (karahmed) Update microcode blacklist David Woodhouse (4): x86/speculation: Update Speculation Control microcode blacklist Revert "x86/speculation: Simplify indirect_branch_prediction_barrier()" KVM: x86: Reduce retpoline performance impact in slot_handle_level_range() x86/speculation: Use IBRS if available before calling into firmware KarimAllah Ahmed (2): X86/nVMX: Properly set spec_ctrl and pred_cmd before merging MSRs KVM/nVMX: Set the CPU_BASED_USE_MSR_BITMAPS if we have a valid L02 MSR bitmap arch/x86/include/asm/apm.h | 6 ++++++ arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/efi.h | 17 +++++++++++++++-- arch/x86/include/asm/nospec-branch.h | 32 ++++++++++++++++++++++++++++---- arch/x86/include/asm/processor.h | 3 --- arch/x86/kernel/cpu/bugs.c | 18 +++++++++++------- arch/x86/kernel/cpu/intel.c | 4 ---- arch/x86/kvm/mmu.c | 10 +++++----- arch/x86/kvm/vmx.c | 7 ++++--- drivers/watchdog/hpwdt.c | 3 +++ 10 files changed, 73 insertions(+), 28 deletions(-) -- 2.7.4