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[209.132.180.67]) by mx.google.com with ESMTP id u6si4690585pfd.236.2018.02.12.08.56.59; Mon, 12 Feb 2018 08:57:14 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=c5Fpb6Du; dkim=pass header.i=@codeaurora.org header.s=default header.b=c5Fpb6Du; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934710AbeBLQBK (ORCPT + 99 others); Mon, 12 Feb 2018 11:01:10 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:42148 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932878AbeBLQBI (ORCPT ); Mon, 12 Feb 2018 11:01:08 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id C5BCA60F76; Mon, 12 Feb 2018 16:01:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1518451267; bh=ySU6G/LHFlInxpO9/fLJ5WF7V8GB3wa8hBSD2diMpE8=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=c5Fpb6DuDfodHm3/Ai4LH1o9V2v+NWQeDe1eUuTba4HppY899bv6KK3gCnA92nPFm z4970ie4wQvzBcbS8/wyu2dFDQl8a63zgqrquzIth10l8Rjd78qGiellRErpth8We4 HZvu1pljW3OuKg6OX+wlMyoGPlTveWv9F81QD4WE= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from localhost (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 4B19F60A4E; Mon, 12 Feb 2018 16:01:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1518451267; bh=ySU6G/LHFlInxpO9/fLJ5WF7V8GB3wa8hBSD2diMpE8=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=c5Fpb6DuDfodHm3/Ai4LH1o9V2v+NWQeDe1eUuTba4HppY899bv6KK3gCnA92nPFm z4970ie4wQvzBcbS8/wyu2dFDQl8a63zgqrquzIth10l8Rjd78qGiellRErpth8We4 HZvu1pljW3OuKg6OX+wlMyoGPlTveWv9F81QD4WE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 4B19F60A4E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org Date: Mon, 12 Feb 2018 16:01:06 +0000 From: Lina Iyer To: Thomas Gleixner Cc: jason@lakedaemon.net, marc.zyngier@arm.com, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, asathyak@codeaurora.org Subject: Re: [PATCH v6 1/2] drivers: irqchip: pdc: Add PDC interrupt controller for QCOM SoCs Message-ID: <20180212160106.GE7084@codeaurora.org> References: <20180209165735.19151-1-ilina@codeaurora.org> <20180209165735.19151-2-ilina@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.2 (2017-12-15) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Feb 12 2018 at 13:40 +0000, Thomas Gleixner wrote: >On Fri, 9 Feb 2018, Lina Iyer wrote: >> +/* >> + * GIC does not handle falling edge or active low. To allow falling edge and >> + * active low interrupts to be handled at GIC, PDC has an inverter that inverts >> + * falling edge into a rising edge and active low into an active high. >> + * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to >> + * set as per the table below. >> + * (polarity, falling edge, rising edge ) POLARITY >> + * 3'b0 00 Level sensitive active low LOW >> + * 3'b0 01 Rising edge sensitive NOT USED >> + * 3'b0 10 Falling edge sensitive LOW >> + * 3'b0 11 Dual Edge sensitive NOT USED >> + * 3'b1 00 Level sensitive active High HIGH >> + * 3'b1 01 Falling Edge sensitive NOT USED >> + * 3'b1 10 Rising edge sensitive HIGH >> + * 3'b1 11 Dual Edge sensitive HIGH >> + */ >> +enum pdc_irq_config_bits { >> + PDC_POLARITY_LOW = 0, >> + PDC_FALLING_EDGE = 2, >> + PDC_POLARITY_HIGH = 4, >> + PDC_RISING_EDGE = 6, >> + PDC_DUAL_EDGE = 7, > >My previous comment about using binary constants still stands. Please >either address review comments or reply at least. Ignoring reviews is not >an option. > I removed them from the enum definitions. Will remove them from the comments as well. Sorry. It was not my intention to ignore any review comments. >Aside of that I really have to ask about the naming of these constants. Are >these names hardware register nomenclature? If yes, they are disgusting. If >no, they are still disgusting, but should be changed to sensible ones, >which just match the IRQ_TYPE naming convention. > > PDC_LEVEL_LOW = 000b, > PDC_EDGE_FALLING = 010b, > .... > > They are named that way in spec :) Will change. >> + switch (type) { >> + case IRQ_TYPE_EDGE_RISING: >> + pdc_type = PDC_RISING_EDGE; >> + type = IRQ_TYPE_EDGE_RISING; > >Whats the point of assigning the same value again? > Failed to notice. Will fix. Thanks, Lina >> + break; >> + case IRQ_TYPE_EDGE_FALLING: >> + pdc_type = PDC_FALLING_EDGE; >> + type = IRQ_TYPE_EDGE_RISING; >> + break; >> + case IRQ_TYPE_EDGE_BOTH: >> + pdc_type = PDC_DUAL_EDGE; >> + break; >> + case IRQ_TYPE_LEVEL_HIGH: >> + pdc_type = PDC_POLARITY_HIGH; >> + type = IRQ_TYPE_LEVEL_HIGH; > >Ditto > >Thanks, > > tglx