Received: by 10.223.185.116 with SMTP id b49csp3664796wrg; Tue, 13 Feb 2018 05:59:33 -0800 (PST) X-Google-Smtp-Source: AH8x2245r60VXlFRhjf0fbziERSfn77cv8wymyrB14yAaH0FXgta4Wndb0GvPTuF86/B8batBB6z X-Received: by 10.101.87.201 with SMTP id q9mr1099013pgr.47.1518530373717; Tue, 13 Feb 2018 05:59:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518530373; cv=none; d=google.com; s=arc-20160816; b=uKY3pEOIvbGE9O0vpJ+9qolYX+TRVy0FnesFr/4mmErxsxaj8ou0I8l6SYMrHHnQPz yv2LpdEHl48J/iMmRKAJOlStfbz99vm89pfhiduzjq9lnRDKBzMcLZH8eIi2+TlQueMJ vg1TqpVciUXXE+8/z2vvlbEsSzcoSifVUxjA7ebhNqNPz0fVvXowg9OMMKUPqIqDFi2v w406Qra3v7PgH1d8ySpf2Q2aCqXGyVzTBCs60NRKg2UOFAkAihFqEo4MyePeRKFMEutn nIm3wG62r4DYkLRkMwvD/UswU55JvCYuekgW3RRatNooOJMsqzwJLDFpknUQvCCCF5tw t5ZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:cc:to:subject:message-id:date:from :references:in-reply-to:mime-version:dkim-signature :arc-authentication-results; bh=YXuCr88dR8+Y7HRy2UpzlUIDGaXrEtpSxTWVwKeFRc0=; b=qbrMR5L+ymMQ38w8iGWMIkRXyy4w71vNb1qcmCl5IUK8QhUwlAiYBMWO8RHcAR2r4B TmarJtfEPNwtIyQYILAOMyc8Hkj1xfU3Rs9q/TeWv1xhx0/p8ESn2D/yQdLFZQ1Zb630 9UXTl4DX+jvZzezjbsyGkktx4gfmqm7Xcg48HUie3T7cSZT1o7ty+ruX2k7qfzaGsQjx Ex+cf2+XUWQPal44pY17RdF454K9L35T2DtVWUiuFvdrAU3PqKlfVWDNboVBaMXIqi8m lHifh7QHh6IWuTAlZCZAdJFAl7QcXgLwJyuApJoxYDylfWGsQRnT7oeJmcJzOJ/xXfJT Q5lA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=esyXta+A; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g33-v6si1509171plb.251.2018.02.13.05.59.17; Tue, 13 Feb 2018 05:59:33 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=esyXta+A; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964990AbeBMN6a (ORCPT + 99 others); Tue, 13 Feb 2018 08:58:30 -0500 Received: from mail-ua0-f196.google.com ([209.85.217.196]:39963 "EHLO mail-ua0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964859AbeBMN62 (ORCPT ); Tue, 13 Feb 2018 08:58:28 -0500 Received: by mail-ua0-f196.google.com with SMTP id t6so11600761ual.7 for ; Tue, 13 Feb 2018 05:58:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=YXuCr88dR8+Y7HRy2UpzlUIDGaXrEtpSxTWVwKeFRc0=; b=esyXta+A+Md6b+gNloloR/igztuoXJZBXAP2LRWBPBRSncmCcrfJENAcNU7ArCVwzV g+3rJIYYgDns3YezOIe9Qp0yo2/YouoxpggngVEBYw74qOVrd0dbA4v8yP28Eryyeubz aMaMUHTCVzbKT/jtw3HIx8WYdwg2t/8A1TxyQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=YXuCr88dR8+Y7HRy2UpzlUIDGaXrEtpSxTWVwKeFRc0=; b=HRcYiw6wRHJoPIW/QnAwworp7nQN69si/5y5W2iVTX3b4mZ9LBo+nF9hpezRudo5yJ WWukv8z+buKiDBcXiNWIfbu/k3zCzAbBBMYlQWGpT3gonkUxdcG+MdNr6ajp3vd61yfZ 4DUyfXnhXNZ+qaHfJe/f9c8C1FutSDNrqBr0RwNcvkck2wM8LeNrkfxKuTLBWneX2NFO Q4rIE0hWaB7KUnKrD6I57tvrYV0H/0nsD/9pbnN0r+mRmd6aahw4Uj6qBZzXmfQ44I0M iQJw7aiZ+EcPRqZk6OkulepsP1IlWXfOK/fjjxSKndR8aDZeRpg9415uYF0LaxZJvD59 AaOg== X-Gm-Message-State: APf1xPDum+9lICWgFgnN69cNPFyFbu3VveBThnQKz/phUcrJPeKsk1MY NUNJcbHF/4EKfvv+e8LEns5Mqmf/yBQ= X-Received: by 10.159.43.143 with SMTP id y15mr1189280uai.96.1518530307739; Tue, 13 Feb 2018 05:58:27 -0800 (PST) Received: from mail-vk0-f50.google.com (mail-vk0-f50.google.com. [209.85.213.50]) by smtp.gmail.com with ESMTPSA id k6sm3825667uag.2.2018.02.13.05.58.27 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 13 Feb 2018 05:58:27 -0800 (PST) Received: by mail-vk0-f50.google.com with SMTP id j204so10850864vke.12 for ; Tue, 13 Feb 2018 05:58:27 -0800 (PST) X-Received: by 10.31.138.72 with SMTP id m69mr1138963vkd.13.1518529994302; Tue, 13 Feb 2018 05:53:14 -0800 (PST) MIME-Version: 1.0 Received: by 10.176.0.68 with HTTP; Tue, 13 Feb 2018 05:52:53 -0800 (PST) In-Reply-To: <906051dd-8898-ec6f-5ad4-3f37716292cf@arm.com> References: <1517999482-17317-1-git-send-email-vivek.gautam@codeaurora.org> <1517999482-17317-4-git-send-email-vivek.gautam@codeaurora.org> <906051dd-8898-ec6f-5ad4-3f37716292cf@arm.com> From: Tomasz Figa Date: Tue, 13 Feb 2018 22:52:53 +0900 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v7 3/6] iommu/arm-smmu: Invoke pm_runtime during probe, add/remove device To: Robin Murphy Cc: Vivek Gautam , "list@263.net:IOMMU DRIVERS" , Joerg Roedel , Rob Herring , Mark Rutland , "Rafael J. Wysocki" , Will Deacon , Rob Clark , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel , freedreno@lists.freedesktop.org, David Airlie , Greg KH , sboyd@codeaurora.org, linux-arm-msm@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Feb 13, 2018 at 9:57 PM, Robin Murphy wrote: > On 13/02/18 08:24, Tomasz Figa wrote: >> >> Hi Vivek, >> >> Thanks for the patch. Please see my comments inline. >> >> On Wed, Feb 7, 2018 at 7:31 PM, Vivek Gautam >> wrote: >>> >>> From: Sricharan R >>> >>> The smmu device probe/remove and add/remove master device callbacks >>> gets called when the smmu is not linked to its master, that is without >>> the context of the master device. So calling runtime apis in those places >>> separately. >>> >>> Signed-off-by: Sricharan R >>> [vivek: Cleanup pm runtime calls] >>> Signed-off-by: Vivek Gautam >>> --- >>> drivers/iommu/arm-smmu.c | 42 >>> ++++++++++++++++++++++++++++++++++++++---- >>> 1 file changed, 38 insertions(+), 4 deletions(-) >>> >>> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c >>> index 9e2f917e16c2..c024f69c1682 100644 >>> --- a/drivers/iommu/arm-smmu.c >>> +++ b/drivers/iommu/arm-smmu.c >>> @@ -913,11 +913,15 @@ static void arm_smmu_destroy_domain_context(struct >>> iommu_domain *domain) >>> struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); >>> struct arm_smmu_device *smmu = smmu_domain->smmu; >>> struct arm_smmu_cfg *cfg = &smmu_domain->cfg; >>> - int irq; >>> + int ret, irq; >>> >>> if (!smmu || domain->type == IOMMU_DOMAIN_IDENTITY) >>> return; >>> >>> + ret = pm_runtime_get_sync(smmu->dev); >>> + if (ret) >>> + return; >> >> >> pm_runtime_get_sync() will return 0 if the device was powered off, 1 >> if it was already/still powered on or runtime PM is not compiled in, >> or a negative value on error, so shouldn't the test be (ret < 0)? >> >> Moreover, I'm actually wondering if it makes any sense to power up the >> hardware just to program it and power it down again. In a system where >> the IOMMU is located within a power domain, it would cause the IOMMU >> block to lose its state anyway. > > > This is generally for the case where the SMMU internal state remains active, > but the programming interface needs to be powered up in order to access it. That's true for Qualcomm SMMU, but I think that would be different for existing users of the driver? > >> Actually, reflecting back on "[PATCH v7 2/6] iommu/arm-smmu: Add >> pm_runtime/sleep ops", perhaps it would make more sense to just >> control the clocks independently of runtime PM? Then, runtime PM could >> be used for real power management, e.g. really powering the block up >> and down, for further power saving. > > > Unfortunately that ends up pretty much unmanageable, because there are > numerous different SMMU microarchitectures with fundamentally different > clock/power domain schemes (multiplied by individual SoC integration > possibilities). Since this is fundamentally a generic architectural driver, > adding explicit clock support would probably make the whole thing about 50% > clock code, with complicated decision trees around every hardware access > calculating which clocks are necessary for a given operation on a given > system. That maintainability aspect is why we've already nacked such a > fine-grained approach in the past. Hmm, I think we are talking about different things here. My suggestion would not add much more code to the driver than this patch does, calls to arm_smmu_enable_clocks() instead of pm_runtime_get_sync() and arm_smmu_disable_clocks() instead of pm_runtime_put(). The implementation of both functions would be a simple call to clk_bulk_ API (possibly even no need to put this into functions, just call directly). Best regards, Tomasz