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[209.132.180.67]) by mx.google.com with ESMTP id 94-v6si44926ple.298.2018.02.13.08.42.52; Tue, 13 Feb 2018 08:43:07 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=NtKac3s6; dkim=pass header.i=@codeaurora.org header.s=default header.b=laQnbadK; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934933AbeBMQmN (ORCPT + 99 others); Tue, 13 Feb 2018 11:42:13 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:47898 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934210AbeBMQmK (ORCPT ); Tue, 13 Feb 2018 11:42:10 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 01BA860F6B; Tue, 13 Feb 2018 16:42:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1518540130; bh=bTNzqeSCC0bOzGouSaDswQbjgZkIN9IFLHLRqLCypA8=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=NtKac3s6hxNRL7TyHw2qqpVzq2whdhPNkf6xrtj80mnyUHOoDQUCZfbhhcbV2RCfw /obyUHAWVDoGhbqrRuKCWjyEBs5c48Zz3l3Fh0gOKcLKiwFEqlgKWwlPLIB4NgSwwl mp0KQkF2gSMOz72hK9APHbh1v5hI6SmSQ8DUYruU= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 67EC360F6B; Tue, 13 Feb 2018 16:42:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1518540128; bh=bTNzqeSCC0bOzGouSaDswQbjgZkIN9IFLHLRqLCypA8=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=laQnbadKZnYVgBs01dbQTT1GGLJQiaLay/Zi2FnlUraskvwzkuO29E/WHYSdLqh4p y4QbXcoSncjUp1d06DAVA3fJfHP3OMoIK9J/ekwQCrv7KzaCx8YRYLNYgbs/los3fG X0qOKFnK4poASxTEgCgkPBYDyPETZUCbFDZsmsMg= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 67EC360F6B Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org Date: Tue, 13 Feb 2018 09:42:05 -0700 From: Jordan Crouse To: Tomasz Figa Cc: Vivek Gautam , Mark Rutland , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, David Airlie , Will Deacon , "Rafael J. Wysocki" , "list@263.net:IOMMU DRIVERS , Joerg Roedel , " , dri-devel , linux-kernel@vger.kernel.org, Rob Herring , Greg KH , freedreno@lists.freedesktop.org, Robin Murphy , sboyd@codeaurora.org, linux-arm-msm@vger.kernel.org Subject: Re: [PATCH v7 6/6] drm/msm: iommu: Replace runtime calls with runtime suppliers Message-ID: <20180213164205.GA7599@jcrouse-lnx.qualcomm.com> Mail-Followup-To: Tomasz Figa , Vivek Gautam , Mark Rutland , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, David Airlie , Will Deacon , "Rafael J. Wysocki" , "list@263.net:IOMMU DRIVERS , Joerg Roedel , " , dri-devel , linux-kernel@vger.kernel.org, Rob Herring , Greg KH , freedreno@lists.freedesktop.org, Robin Murphy , sboyd@codeaurora.org, linux-arm-msm@vger.kernel.org References: <1517999482-17317-1-git-send-email-vivek.gautam@codeaurora.org> <1517999482-17317-7-git-send-email-vivek.gautam@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Feb 13, 2018 at 06:10:38PM +0900, Tomasz Figa wrote: > Hi Vivek, > > Thanks for the patch. Please see my comments inline. > > On Wed, Feb 7, 2018 at 7:31 PM, Vivek Gautam > wrote: > > While handling the concerned iommu, there should not be a > > need to power control the drm devices from iommu interface. > > If these drm devices need to be powered around this time, > > the respective drivers should take care of this. > > > > Replace the pm_runtime_get/put_sync() with > > pm_runtime_get/put_suppliers() calls, to power-up > > the connected iommu through the device link interface. > > In case the device link is not setup these get/put_suppliers() > > calls will be a no-op, and the iommu driver should take care of > > powering on its devices accordingly. > > > > Signed-off-by: Vivek Gautam > > --- > > drivers/gpu/drm/msm/msm_iommu.c | 16 ++++++++-------- > > 1 file changed, 8 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c > > index b23d33622f37..1ab629bbee69 100644 > > --- a/drivers/gpu/drm/msm/msm_iommu.c > > +++ b/drivers/gpu/drm/msm/msm_iommu.c > > @@ -40,9 +40,9 @@ static int msm_iommu_attach(struct msm_mmu *mmu, const char * const *names, > > struct msm_iommu *iommu = to_msm_iommu(mmu); > > int ret; > > > > - pm_runtime_get_sync(mmu->dev); > > + pm_runtime_get_suppliers(mmu->dev); > > ret = iommu_attach_device(iommu->domain, mmu->dev); > > - pm_runtime_put_sync(mmu->dev); > > + pm_runtime_put_suppliers(mmu->dev); > > For me, it looks like a wrong place to handle runtime PM of IOMMU > here. iommu_attach_device() calls into IOMMU driver's attach_device() > callback and that's where necessary runtime PM gets should happen, if > any. In other words, driver A (MSM DRM driver) shouldn't be dealing > with power state of device controlled by driver B (ARM SMMU). This whole thing is confused by the fact that on MSM the GPU and the GPU IOMMU share some of the same clocks and power rail so turning on the GPU also turned on the IOMMU register banks by extension. But if we put that aside the question is who should be responsible for controlling the power in this relationship and there are several good reasons to leave it up to the client device. The most important reason is when we move to the per-instance model where the GPU self-programmings the SMMU registers. In that case, the driver will need to make sure that the SMMU is powered up before submitting the command and then removing the power vote when the commands are done to save energy. Additionally, there might be legitimate reasons in the driver to batch operations - you may wish to attach the device and then map several global buffers immediately - having driver side control prevents several unneeded power transitions. Perhaps the right answer is to do both - allow for the driver to enable the supplier but also do the right power operations at the appropriately places in the IOMMU driver. > This is also important for the reasons I stated in my comments to > "[PATCH v7 1/6] base: power: runtime: Export > pm_runtime_get/put_suppliers". Quoting for everyone's convenience: > > >> There are however cases in which the consumer wants to power-on > >> the supplier, but not itself. > >> E.g., A Graphics or multimedia driver wants to power-on the SMMU > >> to unmap a buffer and finish the TLB operations without powering > >> on itself. > > > >This sounds strange to me. If the SMMU is powered down, wouldn't the > >TLB lose its contents as well (and so no flushing needed)? > > > >Other than that, what kind of hardware operations would be needed > >besides just updating the page tables from the CPU? > > > In other words, the SMMU driver can deal with hardware state based on > return value of pm_runtime_get_sync() or pm_runtime_get_if_in_use() > and decide whether some operations are necessary or not, e.g. > - a state restore is necessary if the domain was powered off, but we > are bringing the master on, > - a flush may not be required when (un)mapping with the domain powered off, > - etc. I agree that there is probably some advanced logic that we can do to conclusively figure out the state of the hardware and improve the behavior. I would love to see the SMMU driver get smarter but for the moment we can't trust it and so we need to force the behavior from the GPU driver. The current code works for a5x and earlier but on sdm845 we can (no longer) treat the GPU and the SMMU as the same device for power purposes so we need this code. If at some point in the future we can start to selectively remove the supplier calls I wouldn't mind one bit. Jordan -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project