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[209.132.180.67]) by mx.google.com with ESMTP id c2-v6si1435603plk.770.2018.02.13.08.55.09; Tue, 13 Feb 2018 08:55:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=nkkJJ1e6; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965100AbeBMQwp (ORCPT + 99 others); Tue, 13 Feb 2018 11:52:45 -0500 Received: from mail-qt0-f172.google.com ([209.85.216.172]:34228 "EHLO mail-qt0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934503AbeBMQwm (ORCPT ); Tue, 13 Feb 2018 11:52:42 -0500 Received: by mail-qt0-f172.google.com with SMTP id d14so4361449qtg.1; Tue, 13 Feb 2018 08:52:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=M312mDxovIkr+pyfcJq/OPWIwyCYnbc3tbCvCGe8AFM=; b=nkkJJ1e6uiSvN6GkKdGYgr4Y4NWKybGSx8kro3hZHP+CIJahMEBGAp+1z+YUZElC39 Lew6gsfB3oCEGucogVf/ijy36XT3QXdZfY36r71h4FvDEypBCL5Yw3ZHmPHHDg8/2Dla xCB+qSBDNb/k25aZ5x1cGpe3R3M8zUyFXNTJkOJwwNd+3lp8N4ee6N9Su91ugcS/F0cS Cc76M3laAnSzPljgNO4T81VsyR8flSA7VUyCCjbMpSrsruBIAumyQszCWmUQ/pCsdV16 uM2zm8/RUdLN9CzcUYFQAxmYAY4dd2FD/Anqwo0OC7ZeBKsLYAaTz2bd+GmnA4nwnqxa cTMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=M312mDxovIkr+pyfcJq/OPWIwyCYnbc3tbCvCGe8AFM=; b=sqRQTa8UAp4XU3d9uJev+FBm2sJw/2sxwcmkqdfQw0KEUmg4odtvmWfshaHZ3IM+7T ZY0MzJudgZE2yA65pt+teYo2lgj5URDcThfAQDdfK6ZNgRih8cSrMm3/IZmXLNJlJC64 1It3w+tzCYa5p/s7HO6JVPYbw5uAajQqpguDlX5rDDs1Yvw+rIM1tZfmYgd59I9Dn3PT XUF1HSsgXrDrbYLpxK8/8bGk0R42JwH/6sGk42n0+3/pdb+7rRps/Z6D8PEMa6RvPmZd EHwbCgwvbtKERLy63/Fuusm4ZKVM5/Q7tdcrvuk5EXk6lhb2TsYS7jYv4qCtlYZSRZQp pnGA== X-Gm-Message-State: APf1xPBsSru0cnvD3BmfmV29rtiljD8aok/tz04SSSCguCDRh0ObPYEx OLSEGpWnCSItDhk1NMUPfdvWb5sSXf4rDeaxH60= X-Received: by 10.200.8.173 with SMTP id v42mr2775809qth.162.1518540762026; Tue, 13 Feb 2018 08:52:42 -0800 (PST) MIME-Version: 1.0 Received: by 10.12.195.82 with HTTP; Tue, 13 Feb 2018 08:52:41 -0800 (PST) In-Reply-To: <20180212044810.23547-1-joel@jms.id.au> References: <20180212044810.23547-1-joel@jms.id.au> From: Andy Shevchenko Date: Tue, 13 Feb 2018 18:52:41 +0200 Message-ID: Subject: Re: [PATCH] serial: 8250: Add Nuvoton NPCM UART To: Joel Stanley Cc: Greg Kroah-Hartman , Rob Herring , Mark Rutland , linux-serial@vger.kernel.org, devicetree , Linux Kernel Mailing List , Tomer Maimon , Avi Fishman , Jeremy Kerr Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Feb 12, 2018 at 6:48 AM, Joel Stanley wrote: > The Nuvoton UART is almost compatible with the 8250 driver when probed > via the 8250_of driver, however it requires some extra configuration > at startup. > + [PORT_NPCM] = { > + .name = "Nuvoton 16550", > + .fifo_size = 16, > + .tx_loadsz = 16, > + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | > + UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, > + .rxtrig_bytes = {1, 4, 8, 14}, > + .flags = UART_CAP_FIFO, > + Redundant. > + }, > + /* > + * Nuvoton calls the scratch register 'UART_TOR' (timeout > + * register). Enable it, and set TIOC (timeout interrupt > + * comparator) to be 0x20 for correct operation. > + */ > + serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20); > +/* Nuvoton NPCM UARTs have a custom divisor calculation */ > + return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2; Is there any link to datasheet? > +/* Nuvoton UART */ > +#define PORT_NPCM 118 We have gaps there. #40 is perfect place for this one. > +/* Nuvoton NPCM timeout register */ > +#define UART_NPCM_TOR 7 > +#define UART_NPCM_TOIE BIT(7) /* Timeout Interrupt Enable */ -- With Best Regards, Andy Shevchenko