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[209.132.180.67]) by mx.google.com with ESMTP id p11si3007166pfl.310.2018.02.14.03.35.53; Wed, 14 Feb 2018 03:36:08 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kapsi.fi header.s=20161220 header.b=PG7cTZkT; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S967483AbeBNLfH (ORCPT + 99 others); Wed, 14 Feb 2018 06:35:07 -0500 Received: from mail.kapsi.fi ([91.232.154.25]:56589 "EHLO mail.kapsi.fi" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S967355AbeBNLfF (ORCPT ); Wed, 14 Feb 2018 06:35:05 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=kapsi.fi; s=20161220; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:MIME-Version:Date:Message-ID:From:Cc:References:To:Subject; bh=BMbU5j2vjdDk81+QOFwAdkzC1CvmiYiC3K9knfAbklg=; b=PG7cTZkTr+2U0O8rJzNYttxDlLdT4yoLLEZIIrStbEe+VCZ1HYk+CGb5Wy27Xz3hR6M199+wU4hAuZ/SVNzp9b38RovWgGKHuEo7vryWb9+knFHbfOvpM2EEEbEDjS68QyBWJAYqJocE+N8RxGmzZVbLfKt9bBqiIG3KRgnifgCcvl7Gku7/zQEvZe7j0tPwhLv1Um2yTOjZMKUVTsB3ddvUcOX6Z60EA6Z27+e3KScHZk8Y09HvQsAbrMMRedOs+ftxKKI4bbnQCY87n67FqkmvS9iIJHxFQnNWH5sY+8JGfIG0iLe7JrscgxG56RYSkGnFJ+/36JjMGYAhG//0UA==; Received: from [62.209.167.43] (helo=[10.21.26.144]) by mail.kapsi.fi with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.84_2) (envelope-from ) id 1elvL4-0002hH-TV; Wed, 14 Feb 2018 13:35:02 +0200 Subject: Re: [PATCH v2 6/7] arm64: tegra: Add Tegra194 chip device tree To: Marc Zyngier , Mikko Perttunen , thierry.reding@gmail.com, jonathanh@nvidia.com, robh+dt@kernel.org, mark.rutland@arm.com References: <1517901757-15353-1-git-send-email-mperttunen@nvidia.com> <1517901757-15353-7-git-send-email-mperttunen@nvidia.com> <458ba9f9-d703-9edf-8e7b-bc9d0f0ef0cc@arm.com> Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, talho@nvidia.com, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org From: Mikko Perttunen Message-ID: Date: Wed, 14 Feb 2018 13:34:58 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 In-Reply-To: <458ba9f9-d703-9edf-8e7b-bc9d0f0ef0cc@arm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 62.209.167.43 X-SA-Exim-Mail-From: cyndis@kapsi.fi X-SA-Exim-Scanned: No (on mail.kapsi.fi); SAEximRunCond expanded to false Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 07.02.2018 12:21, Marc Zyngier wrote: > Hi Mikko, > > On 06/02/18 07:22, Mikko Perttunen wrote: >> Add the chip-level device tree, including binding headers, for the >> NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices >> are initially available, enough to boot to UART console. >> >> Signed-off-by: Mikko Perttunen >> --- >> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 342 +++++++++++++ >> include/dt-bindings/clock/tegra194-clock.h | 664 +++++++++++++++++++++++++ >> include/dt-bindings/gpio/tegra194-gpio.h | 59 +++ >> include/dt-bindings/power/tegra194-powergate.h | 49 ++ >> include/dt-bindings/reset/tegra194-reset.h | 166 +++++++ >> 5 files changed, 1280 insertions(+) >> create mode 100644 arch/arm64/boot/dts/nvidia/tegra194.dtsi >> create mode 100644 include/dt-bindings/clock/tegra194-clock.h >> create mode 100644 include/dt-bindings/gpio/tegra194-gpio.h >> create mode 100644 include/dt-bindings/power/tegra194-powergate.h >> create mode 100644 include/dt-bindings/reset/tegra194-reset.h >> >> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi >> new file mode 100644 >> index 000000000000..dda28d758cab >> --- /dev/null >> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi > > [...] > >> + gic: interrupt-controller@3881000 { >> + compatible = "arm,gic-400"; >> + #interrupt-cells = <3>; >> + interrupt-controller; >> + reg = <0x03881000 0x1000>, >> + <0x03882000 0x2000>; > > You're missing the GICH and GICV regions here. > >> + interrupts = > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; >> + interrupt-parent = <&gic>; >> + }; > Thanks, > > M. > Thanks, fixed. Mikko