Received: by 10.223.185.116 with SMTP id b49csp640383wrg; Wed, 14 Feb 2018 04:49:40 -0800 (PST) X-Google-Smtp-Source: AH8x224qwhTorObDp4/vNJAPKApnzA4vL/c6tqwWSarW1sd7syPf0h2qWvckGFgzqLtD5FUb/hey X-Received: by 2002:a17:902:3a3:: with SMTP id d32-v6mr4414256pld.219.1518612579946; Wed, 14 Feb 2018 04:49:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518612579; cv=none; d=google.com; s=arc-20160816; b=wkgZb4brtnoECSxowp9eWfCb+srt893EFd9lk6Ovrx0HWnaUYaeAYddd/w6s7lTpyD xQJRJCaVqTdJ7TeYEKjs/x1ibWKIgQWadXO/+D+mMB8IWiZnSM7yd2bWvNelxLziRMZj pzZPCMFPL6Hz5fu7bK2BibsPzTAgZUG58+u2oveYczs/xixuQJpg2ffp5BWuPirkUJGd hskKUqOmAn6vqVWwp/nID9S5/bX5TBGV4JEZtdlenIUeH1e1kuWdGRKhGWYrjzDCcALw LS2vdD0VZhiHDVppNEIJ8nKQlqKcxnUdRzqPnYBxPR3lu/seU8w47Fy3LlGUs2UiLvrS ukpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:cc:to:subject:message-id:date:from :references:in-reply-to:mime-version:dkim-signature :arc-authentication-results; bh=Rg0d+UKu2kdgmGDClemalHXIaBB27I6c/XuXCdNFZ3o=; b=ibdtm7AZmrDDpvulnM2AcA/WzVLaugSmmQ70ywSrXHrzRNgHg7un2MBqfEMlBTpjog aJtH69IXWc5cVbj7+48tQ8BTOm2li7tRb8fvBiHhfxwQAA/4lgLClLR22b4b74Fmtrwv cYvNi4NBGyLumSIWppGlLoCPCF+402IPACB+ShmvtZRH6Kn7dEIrHd5dEg8mF+I0Oscw eodi2YBcFERu137ZXoAaC6j1HxLmyDuncwi65TUgpBcv6S9z6nMOWgKH9vdn+ErZ+qmh jSNzslCJ/WeO6zhOFwEAYoXjdiEi8/6L2SkdSE/qOmuhi6gjW6wX0p9w9T+q+DF8wUUi 0e1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=MWe/JZ2H; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y7-v6si1591697pln.220.2018.02.14.04.49.25; Wed, 14 Feb 2018 04:49:39 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=MWe/JZ2H; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030228AbeBNMsc (ORCPT + 99 others); Wed, 14 Feb 2018 07:48:32 -0500 Received: from mail-qk0-f194.google.com ([209.85.220.194]:36194 "EHLO mail-qk0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030215AbeBNMs3 (ORCPT ); Wed, 14 Feb 2018 07:48:29 -0500 Received: by mail-qk0-f194.google.com with SMTP id 15so26453109qkl.3; Wed, 14 Feb 2018 04:48:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=Rg0d+UKu2kdgmGDClemalHXIaBB27I6c/XuXCdNFZ3o=; b=MWe/JZ2HcJ29PiEIXh38quR6G8g4V7WYA6mhzmg9fLugZIbGMBjDy09Y9P/Zd7Y8cy NIc8Q//7Y4G8MBrFt7XQHX+cyKdRBzilRycslK0mEnUsM5SYuUGKVaXaAk6FPsJebBJE faTnS0AaxgIRPpw76hzc/1tn99v+QskWYQQP4CXmyQwrkyexbNVw4+ZmtmIPMQmZWhsm blyT+/yPkn81wZWPhMWZ6crh1JcJUJrEm9gDjQ+L9DjnEUTXanLGRILMySdFOzFskVe/ ljAWcyAFkhEV6QuquiK2MbtMbH/+qeMg7vzEIvh4eFu5XeSZOgmev/CT2tVig3vFvcsv BNcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:sender:in-reply-to:references:from :date:message-id:subject:to:cc; bh=Rg0d+UKu2kdgmGDClemalHXIaBB27I6c/XuXCdNFZ3o=; b=mOHIb/9VoC46wuDUKDvAmk1a5mP5Zy7VGBawFX1fhZ9qITc2RUlGFU8wB5atZJRYHh 6YXNdHeB4kAx3xXCmpD2/ASRu7R7e+eI1SGJvQPN1Pcr8jr2hGAwucnMesOwib0QVu6F Im+T9vd6hYWOvZaQssc1TuZFXsYBk6qEq1fHYyk2xaS642r20mdPeTyrv790fMh79LdX x4YjLzfCY3CBTuvLSlrO1gXq3YHDX5rd+TKZ1NDdqJMNYmh2uGNqGeibqDns5BJ4/O7/ EeL2IIO7s7S3VOE1CnNsm5i8C6/NmFY8EmUOzn+VCGqvB5hGI3ne3Q4NnDt8CbboZPpr aOeg== X-Gm-Message-State: APf1xPBFabjW358GCP1D1i1MEQ9J4Mq9iU9whRmFWtYHE/NTm40shLcM Mp/Gkj2Iri7eJ2gnWE0Zk7Lc44ewF3x4ctBtvqM= X-Received: by 10.55.17.75 with SMTP id b72mr7180918qkh.337.1518612508695; Wed, 14 Feb 2018 04:48:28 -0800 (PST) MIME-Version: 1.0 Received: by 10.200.47.219 with HTTP; Wed, 14 Feb 2018 04:48:27 -0800 (PST) In-Reply-To: <1518515162-23663-4-git-send-email-jacopo+renesas@jmondi.org> References: <1518515162-23663-1-git-send-email-jacopo+renesas@jmondi.org> <1518515162-23663-4-git-send-email-jacopo+renesas@jmondi.org> From: Geert Uytterhoeven Date: Wed, 14 Feb 2018 13:48:27 +0100 X-Google-Sender-Auth: aKPso2zcEcApTbmpBJz7N4Z0Nyo Message-ID: Subject: Re: [PATCH 03/15] soc: renesas: Add R-Car M3-N support To: Jacopo Mondi Cc: Simon Horman , Magnus Damm , Rob Herring , Mark Rutland , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-arm-kernel@lists.infradead.org, Linux-Renesas , Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jacopo, Thanks for your patch! On Tue, Feb 13, 2018 at 10:45 AM, Jacopo Mondi wrote: > Add support for R-Car M3-N (r8a77965) power areas and reset. > M3-N power areas are identical to M3-W ones, so just copy and rename > them. They are not identical: - M3-N does not have the CA53-related areas, - M3-W does not have A3VP, - M3-N does not have A2VC0 (M3-W also doesn't, according to latest datasheet?). The datasheet also mentions A3SH, without further info about the register block. I think we need to bring this up with Renesas. > .../bindings/power/renesas,rcar-sysc.txt | 1 + > .../devicetree/bindings/reset/renesas,rst.txt | 1 + > drivers/soc/renesas/Kconfig | 9 ++++-- > drivers/soc/renesas/Makefile | 1 + > drivers/soc/renesas/r8a77965-sysc.c | 37 ++++++++++++++++++++++ > drivers/soc/renesas/rcar-rst.c | 1 + > drivers/soc/renesas/rcar-sysc.c | 3 ++ > drivers/soc/renesas/rcar-sysc.h | 1 + > drivers/soc/renesas/renesas-soc.c | 8 +++++ > include/dt-bindings/power/r8a77965-sysc.h | 31 ++++++++++++++++++ > 10 files changed, 91 insertions(+), 2 deletions(-) > create mode 100644 drivers/soc/renesas/r8a77965-sysc.c > create mode 100644 include/dt-bindings/power/r8a77965-sysc.h The maintainer may ask you to split this patch by functionality... > --- /dev/null > +++ b/drivers/soc/renesas/r8a77965-sysc.c > @@ -0,0 +1,37 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Renesas R-Car M3-N System Controller > + * Copyright (C) 2018 Jacopo Mondi > + * > + * Based on Renesas R-Car M3-W System Controller > + * Copyright (C) 2016 Glider bvba > + */ > + > +#include > +#include > + > +#include > + > +#include "rcar-sysc.h" > + > +static const struct rcar_sysc_area r8a77965_areas[] __initconst = { > + { "always-on", 0, 0, R8A77965_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, > + { "ca57-scu", 0x1c0, 0, R8A77965_PD_CA57_SCU, R8A77965_PD_ALWAYS_ON, > + PD_SCU }, > + { "ca57-cpu0", 0x80, 0, R8A77965_PD_CA57_CPU0, R8A77965_PD_CA57_SCU, > + PD_CPU_NOCR }, > + { "ca57-cpu1", 0x80, 1, R8A77965_PD_CA57_CPU1, R8A77965_PD_CA57_SCU, > + PD_CPU_NOCR }, > + { "cr7", 0x240, 0, R8A77965_PD_CR7, R8A77965_PD_ALWAYS_ON }, > + { "a3vc", 0x380, 0, R8A77965_PD_A3VC, R8A77965_PD_ALWAYS_ON }, > + { "a2vc0", 0x3c0, 0, R8A77965_PD_A2VC0, R8A77965_PD_A3VC }, M3-N (and M3-W) does not have A2VC0? > + { "a2vc1", 0x3c0, 1, R8A77965_PD_A2VC1, R8A77965_PD_A3VC }, > + { "3dg-a", 0x100, 0, R8A77965_PD_3DG_A, R8A77965_PD_ALWAYS_ON }, > + { "3dg-b", 0x100, 1, R8A77965_PD_3DG_B, R8A77965_PD_3DG_A }, > + { "a3ir", 0x180, 0, R8A77965_PD_A3IR, R8A77965_PD_ALWAYS_ON }, A3VP is missing? > +}; > + > +const struct rcar_sysc_info r8a77965_sysc_info __initconst = { > + .areas = r8a77965_areas, > + .num_areas = ARRAY_SIZE(r8a77965_areas), > +}; > --- /dev/null > +++ b/include/dt-bindings/power/r8a77965-sysc.h > @@ -0,0 +1,31 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (C) 2018 Jacopo Mondi > + * Copyright (C) 2016 Glider bvba > + */ > + > +#ifndef __DT_BINDINGS_POWER_R8A77965_SYSC_H__ > +#define __DT_BINDINGS_POWER_R8A77965_SYSC_H__ > + > +/* > + * These power domain indices match the numbers of the interrupt bits > + * representing the power areas in the various Interrupt Registers > + * (e.g. SYSCISR, Interrupt Status Register) > + */ > + > +#define R8A77965_PD_CA57_CPU0 0 > +#define R8A77965_PD_CA57_CPU1 1 > +#define R8A77965_PD_A3VP 9 > +#define R8A77965_PD_CA57_SCU 12 > +#define R8A77965_PD_CR7 13 > +#define R8A77965_PD_A3VC 14 > +#define R8A77965_PD_3DG_A 17 > +#define R8A77965_PD_3DG_B 18 > +#define R8A77965_PD_A3IR 24 > +#define R8A77965_PD_A2VC0 25 M3-N (and M3-W) does not have A2VC0? > +#define R8A77965_PD_A2VC1 26 > + > +/* Always-on power area */ > +#define R8A77965_PD_ALWAYS_ON 32 > + > +#endif /* __DT_BINDINGS_POWER_R8A77965_SYSC_H__ */ Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds