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Date:   Wed, 14 Feb 2018 09:04:12 -0800
In-Reply-To: <1518624432-15110-1-git-send-email-d.schultz@phytec.de>
References: <1518624432-15110-1-git-send-email-d.schultz@phytec.de>
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Subject: Re: [PATCH v3 1/2] net: phy: dp83867: Add binding for the CLK_OUT pin muxing option
To:     Daniel Schultz <d.schultz@phytec.de>, robh+dt@kernel.org,
        mark.rutland@arm.com, andrew@lunn.ch, netdev@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
CC:     w.egorov@phytec.de
From:   Florian Fainelli <f.fainelli@gmail.com>
Message-ID: <4CCCD320-91E4-4FCD-A467-FD323BAB2427@gmail.com>
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

On February 14, 2018 8:07:11 AM PST, Daniel Schultz <d=2Eschultz@phytec=2Ed=
e> wrote:
>From: Wadim Egorov <w=2Eegorov@phytec=2Ede>
>
>The DP83867 has a muxing option for the CLK_OUT pin=2E It is possible
>to set CLK_OUT for different channels=2E
>Create a binding to select a specific clock for CLK_OUT pin=2E
>
>Signed-off-by: Wadim Egorov <w=2Eegorov@phytec=2Ede>
>Signed-off-by: Daniel Schultz <d=2Eschultz@phytec=2Ede>
>---
>Changes:
>	v2:
>	  Added check if clk_output_sel has a valid value
>	  Only write the clock ouput register if a musing is desired
>	v3:
>	  -
>
> drivers/net/phy/dp83867=2Ec            | 19 +++++++++++++++++++
> include/dt-bindings/net/ti-dp83867=2Eh | 14 ++++++++++++++
> 2 files changed, 33 insertions(+)
>
>diff --git a/drivers/net/phy/dp83867=2Ec b/drivers/net/phy/dp83867=2Ec
>index c1ab976=2E=2Ea862194 100644
>--- a/drivers/net/phy/dp83867=2Ec
>+++ b/drivers/net/phy/dp83867=2Ec
>@@ -75,6 +75,8 @@
>=20
> #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX	0x0
> #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN	0x1f
>+#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK	(0x1f << 8)
>+#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT	8
>=20

Nit: it looks like you could use the shift constant you define for definin=
g the mask as well=2E

Other than that:

Reviewed-by: Florian Fainelli <f=2Efainelli@gmail=2Ecom>

--=20
Florian