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[209.132.180.67]) by mx.google.com with ESMTP id v27si541799pfi.191.2018.02.14.22.06.52; Wed, 14 Feb 2018 22:07:06 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Pc3ABbbJ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755010AbeBOGFx (ORCPT + 99 others); Thu, 15 Feb 2018 01:05:53 -0500 Received: from fllnx210.ext.ti.com ([198.47.19.17]:63814 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754816AbeBOGD6 (ORCPT ); Thu, 15 Feb 2018 01:03:58 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id w1F63BLS025407; Thu, 15 Feb 2018 00:03:11 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1518674591; bh=yh6Yc/IOGuZ90vEgsDcoPPsfZCoSPqJzLCY3sFuPZIU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Pc3ABbbJjyCbcRW58sEMxt4nl/GeiVTr+J16l5zgcxhqGQtXANPEi/25hflMqxg9L CKuObsVr8kOhvY2rhA/a0PXor7hTzNSzVsMUQ75gPaSm6EMEa5pM4Lquonif+oKIzc Nsz32fjJuxdz0UeuuEjGV8xPlP4HgCQ6Gop6Q+5E= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w1F63BsH030305; Thu, 15 Feb 2018 00:03:11 -0600 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Thu, 15 Feb 2018 00:03:11 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Thu, 15 Feb 2018 00:03:11 -0600 Received: from ula0393675.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w1F62uf2020364; Thu, 15 Feb 2018 00:03:06 -0600 From: Keerthy To: , , , CC: , , , , , , , , , , , , Subject: [PATCH v11 02/10] arm: omap: timer: Wrap the inline functions under OMAP2PLUS define Date: Thu, 15 Feb 2018 11:31:43 +0530 Message-ID: <1518674511-26421-3-git-send-email-j-keerthy@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1518674511-26421-1-git-send-email-j-keerthy@ti.com> References: <1518674511-26421-1-git-send-email-j-keerthy@ti.com> MIME-Version: 1.0 Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Wrap the inline functions under OMAP2PLUS/OMAP1 defines. This patch also inlines omap_dm_timer_get_fclk function for non OMAP1 Config. Signed-off-by: Keerthy Tested-by: Ladislav Michl Reviewed-by: Sebastian Reichel --- arch/arm/plat-omap/include/plat/dmtimer.h | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 8b7d8a6..831174f 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -132,7 +132,16 @@ struct omap_dm_timer { int omap_dm_timer_get_irq(struct omap_dm_timer *timer); u32 omap_dm_timer_modify_idlect_mask(u32 inputmask); + +#ifndef CONFIG_ARCH_OMAP1 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer); +#else +static inline +struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) +{ + return NULL; +} +#endif int omap_dm_timer_trigger(struct omap_dm_timer *timer); int omap_dm_timer_start(struct omap_dm_timer *timer); @@ -272,6 +281,12 @@ struct omap_dm_timer { #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \ (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT)) +/* + * The below are inlined to optimize code size for system timers. Other code + * should not need these at all, see + * include/linux/platform_data/pwm_omap_dmtimer.h + */ +#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2PLUS) static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg, int posted) { @@ -410,5 +425,5 @@ static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer, { writel_relaxed(value, timer->irq_stat); } - +#endif /* CONFIG_ARCH_OMAP1 || CONFIG_ARCH_OMAP2PLUS */ #endif /* __ASM_ARCH_DMTIMER_H */ -- 1.9.1