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[209.132.180.67]) by mx.google.com with ESMTP id h91-v6si2163229pld.202.2018.02.15.00.23.15; Thu, 15 Feb 2018 00:23:29 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755157AbeBOIWH (ORCPT + 99 others); Thu, 15 Feb 2018 03:22:07 -0500 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:45066 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754906AbeBOIVO (ORCPT ); Thu, 15 Feb 2018 03:21:14 -0500 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w1F8IYaX008197; Thu, 15 Feb 2018 09:20:48 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2g1q327t55-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 15 Feb 2018 09:20:48 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 3A24C34; Thu, 15 Feb 2018 08:20:48 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 1AC5B2559; Thu, 15 Feb 2018 08:20:48 +0000 (GMT) Received: from SAFEX1HUBCAS24.st.com (10.75.90.94) by SAFEX1HUBCAS21.st.com (10.75.90.44) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 15 Feb 2018 09:20:48 +0100 Received: from localhost (10.129.6.172) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 15 Feb 2018 09:20:46 +0100 From: Philippe Cornu To: Rob Herring , Mark Rutland , Russell King , Maxime Coquelin , Alexandre Torgue , , , CC: Benjamin Gaignard , Yannick Fertre , Philippe Cornu , "Vincent Abriou" Subject: [PATCH 2/3] ARM: dts: stm32: Add new stm32f469 dtsi file with mipi dsi Date: Thu, 15 Feb 2018 09:20:13 +0100 Message-ID: <20180215082014.30383-3-philippe.cornu@st.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180215082014.30383-1-philippe.cornu@st.com> References: <20180215082014.30383-1-philippe.cornu@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.129.6.172] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2018-02-15_03:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In the stm32f4 family, mipi dsi is only supported on stm32f469. So add a new stm32f469 dtsi file & add mipi dsi support inside. Signed-off-by: Philippe Cornu --- arch/arm/boot/dts/stm32f469.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 arch/arm/boot/dts/stm32f469.dtsi diff --git a/arch/arm/boot/dts/stm32f469.dtsi b/arch/arm/boot/dts/stm32f469.dtsi new file mode 100644 index 000000000000..5ae5213f68cb --- /dev/null +++ b/arch/arm/boot/dts/stm32f469.dtsi @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* Copyright (C) STMicroelectronics 2017 - All Rights Reserved */ + +#include "stm32f429.dtsi" + +/ { + soc { + dsi: dsi@40016c00 { + compatible = "st,stm32-dsi"; + reg = <0x40016c00 0x800>; + interrupts = <92>; + resets = <&rcc STM32F4_APB2_RESET(DSI)>; + reset-names = "apb"; + clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>; + clock-names = "pclk", "ref"; + status = "disabled"; + }; + }; +}; -- 2.15.1