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[209.132.180.67]) by mx.google.com with ESMTP id w3si677564pgq.415.2018.02.15.05.06.07; Thu, 15 Feb 2018 05:06:21 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1032703AbeBONEo (ORCPT + 99 others); Thu, 15 Feb 2018 08:04:44 -0500 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:52313 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030561AbeBOND7 (ORCPT ); Thu, 15 Feb 2018 08:03:59 -0500 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w1FCwxmY008406; Thu, 15 Feb 2018 14:03:27 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2g1q32925a-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 15 Feb 2018 14:03:27 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id DBF8D38; Thu, 15 Feb 2018 13:03:26 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 95AA54E34; Thu, 15 Feb 2018 13:03:26 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by SAFEX1HUBCAS21.st.com (10.75.90.44) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 15 Feb 2018 14:03:26 +0100 Received: from localhost (10.201.23.65) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 15 Feb 2018 14:03:26 +0100 From: Lionel Debieve To: Matt Mackall , Herbert Xu , Arnd Bergmann , Greg Kroah-Hartman , Maxime Coquelin , Alexandre Torgue , Rob Herring , , , CC: Benjamin Gaignard , Ludovic Barre Subject: [PATCH Resend 3/5] hwrng: stm32 - allow disable clock error detection Date: Thu, 15 Feb 2018 14:03:10 +0100 Message-ID: <20180215130312.23612-4-lionel.debieve@st.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180215130312.23612-1-lionel.debieve@st.com> References: <20180215130312.23612-1-lionel.debieve@st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.201.23.65] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2018-02-15_05:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a new property that allow to disable the clock error detection which is required when the clock source selected is out of specification (which is not mandatory). Signed-off-by: Lionel Debieve --- drivers/char/hw_random/stm32-rng.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/char/hw_random/stm32-rng.c b/drivers/char/hw_random/stm32-rng.c index 83c695938a2d..709a8d061be3 100644 --- a/drivers/char/hw_random/stm32-rng.c +++ b/drivers/char/hw_random/stm32-rng.c @@ -26,6 +26,7 @@ #define RNG_CR 0x00 #define RNG_CR_RNGEN BIT(2) +#define RNG_CR_CED BIT(5) #define RNG_SR 0x04 #define RNG_SR_SEIS BIT(6) @@ -48,6 +49,7 @@ struct stm32_rng_private { void __iomem *base; struct clk *clk; struct reset_control *rst; + bool ced; }; static int stm32_rng_read(struct hwrng *rng, void *data, size_t max, bool wait) @@ -101,7 +103,11 @@ static int stm32_rng_init(struct hwrng *rng) if (err) return err; - writel_relaxed(RNG_CR_RNGEN, priv->base + RNG_CR); + if (priv->ced) + writel_relaxed(RNG_CR_RNGEN, priv->base + RNG_CR); + else + writel_relaxed(RNG_CR_RNGEN | RNG_CR_CED, + priv->base + RNG_CR); /* clear error indicators */ writel_relaxed(0, priv->base + RNG_SR); @@ -149,6 +155,8 @@ static int stm32_rng_probe(struct platform_device *ofdev) reset_control_deassert(priv->rst); } + priv->ced = of_property_read_bool(np, "clock-error-detect"); + dev_set_drvdata(dev, priv); priv->rng.name = dev_driver_string(dev), -- 2.15.1