Received: by 10.223.185.116 with SMTP id b49csp2122635wrg; Thu, 15 Feb 2018 06:57:39 -0800 (PST) X-Google-Smtp-Source: AH8x22484G4dluFyvOU7zsIJSV4oJ/RHAfwqgaFygt4nP5wqVIvtjNZhPQblZL7HNDxIjwWSzzRz X-Received: by 2002:a17:902:5902:: with SMTP id o2-v6mr2724988pli.79.1518706659100; Thu, 15 Feb 2018 06:57:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518706659; cv=none; d=google.com; s=arc-20160816; b=D4pDR655vfeh3iqLtuySyACt6ln1FG5lijHirl2/pIK+iF4ZMqNpBUiF3paGlyi+Tl kNaEqGmESvnMqCcFkjNr70uJCiQmMmbQ8SfIk9tNuPTU9C2mlp9ma5YuXmq96KmundDs 4BS8vVyTI6xEsFIkHfpi5cwyeuabfINEJ27Ueswk7oe18/RtJ6lXz6DzoZX5+NuUCoe8 PsKHg6pEJAl1y35VV4r9qNSyz0gK8rVf3IFI97AfgnlJS2daGN9peeaUErHz9thkBPVq GTXCGmCuUgyQJh+U+J2XbJSpO8fAPBIVYLQ/TQZPWRg+2cgJcRDMY+WwprLpMkTfdKh1 qekw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=uBQzV0QVHrU5uPymLzTC6ItfoGpDMKRgm5pvQWtDKiU=; b=df32OcuxoHW8IFehUmDKqBxY0kEU8Z4G0eJ3QpmERNhj6uOZW4JSE3cDZ93UB1Z15y oMhhMcTh1/rqv+jWRIM+UDKf0Z8594WPdPIc5OhXE3eVP07wABXtSsceIXe8+dRAplwQ eF/J3VbhQ5spxP+t7CcOpO70073uDHIRlm3KpISi0ix3SyANH8+J3Cj+TFoVsA7FNqH/ l3RGY9CTQkt7h6UXTtUTovdG6736030rZjSX6GpnTjz+iY6eoDOyQnnMKgrrvL9Qwq+5 xpOH4HKlwCkOhOvnpHfvcd7f7Iaam0TKFfrnB7la3SowxOoChOIZBPrfnDjw2MpmPcQc XIQg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b1si1986531pgu.805.2018.02.15.06.57.24; Thu, 15 Feb 2018 06:57:39 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1033567AbeBOOxO (ORCPT + 99 others); Thu, 15 Feb 2018 09:53:14 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:14848 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1032957AbeBOOxM (ORCPT ); Thu, 15 Feb 2018 09:53:12 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Thu, 15 Feb 2018 06:53:19 -0800 Received: from HQMAIL103.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 15 Feb 2018 06:53:12 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 15 Feb 2018 06:53:12 -0800 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 15 Feb 2018 14:53:12 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1347.2 via Frontend Transport; Thu, 15 Feb 2018 14:53:12 +0000 Received: from mperttunen-lnx.Nvidia.com (Not Verified[10.21.26.144]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 15 Feb 2018 06:53:11 -0800 From: Mikko Perttunen To: , , , CC: , , , , , Mikko Perttunen Subject: [PATCH v3 0/7] Initial support for NVIDIA Tegra194 Date: Thu, 15 Feb 2018 16:51:59 +0200 Message-ID: <20180215145206.24775-1-mperttunen@nvidia.com> X-Mailer: git-send-email 2.16.1 X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello everyone, this series adds initial support for the NVIDIA Tegra194 "Xavier" system-on-chip. Initially UART, I2C, SDMMC, as well as the PMIC are supported, allowing booting to a console. The changes consist almost completely of the new device trees, however some fixes are required in the BPMP driver to support the new channel layout in Tegra194. The series has been tested on Tegra186 (Jetson TX2) and Tegra194 (P2972). Cheers, Mikko Mikko Perttunen (7): firmware: tegra: Simplify channel management soc/tegra: Add Tegra194 SoC configuration option soc/tegra: pmc: Add Tegra194 compatibility string dt-bindings: tegra: Add missing chips and NVIDIA boards dt-bindings: tegra: Add documentation for nvidia,tegra194-pmc arm64: tegra: Add Tegra194 chip device tree arm64: tegra: Add device tree for the Tegra194 P2972-0000 board Documentation/devicetree/bindings/arm/tegra.txt | 16 + .../bindings/arm/tegra/nvidia,tegra186-pmc.txt | 2 + arch/arm64/boot/dts/nvidia/Makefile | 1 + arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 248 ++++++++ arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 16 + arch/arm64/boot/dts/nvidia/tegra194.dtsi | 344 +++++++++++ arch/arm64/configs/defconfig | 1 + drivers/firmware/tegra/bpmp.c | 142 ++--- drivers/soc/tegra/Kconfig | 10 + drivers/soc/tegra/pmc.c | 1 + include/dt-bindings/clock/tegra194-clock.h | 653 +++++++++++++++++++++ include/dt-bindings/gpio/tegra194-gpio.h | 64 ++ include/dt-bindings/power/tegra194-powergate.h | 38 ++ include/dt-bindings/reset/tegra194-reset.h | 155 +++++ include/soc/tegra/bpmp.h | 4 +- 15 files changed, 1615 insertions(+), 80 deletions(-) create mode 100644 arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi create mode 100644 arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts create mode 100644 arch/arm64/boot/dts/nvidia/tegra194.dtsi create mode 100644 include/dt-bindings/clock/tegra194-clock.h create mode 100644 include/dt-bindings/gpio/tegra194-gpio.h create mode 100644 include/dt-bindings/power/tegra194-powergate.h create mode 100644 include/dt-bindings/reset/tegra194-reset.h -- 2.16.1