Received: by 10.223.185.116 with SMTP id b49csp2610540wrg; Thu, 15 Feb 2018 14:37:11 -0800 (PST) X-Google-Smtp-Source: AH8x226Gg31AjIm9LaN1l3wJ3FDNc/nYsA8t0DKLR43aWdH9zjnZ1xktGx9kdqJjxla0cjRcX4+G X-Received: by 10.98.8.141 with SMTP id 13mr4038673pfi.213.1518734231686; Thu, 15 Feb 2018 14:37:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518734231; cv=none; d=google.com; s=arc-20160816; b=ofeZ70JcQ+rmOnkXVfMA6qHdTheZzSMXUEKnmJxlsv4PmcvMP7eydH1Efk4SkH3M0M 6dDTH/t3OMVYT+iZ57MyH748cAF/VyBRhIOhZxet+nvJ86FIduAcAqQ5EUTZYz82TBfK eK4qcib+C70ujJTrNDwt4xJCxOb8FxcvWz264A833N+uCUT0yBWIxn0g/gl9oeCfWVWN ViMo5PHdrQgl4X9bWmsY674SUJGw3CG6Q0I0MRaQmHSG51aXz5uKNLBfKjFx8OjnLNiA TtJRO1CBvA6i7Yfeurw4+Gx8diA/3GIJ240IztvJoQCqorHpxtsHU6H2l78AYAha0Mmx rjpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:user-agent:references :in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=UerAKAiHtYecZSlLe+6AVyhsLsFNUs36FgwB5yKQQ8c=; b=JTdKPu2WBCk/Tflk9Nt/7eY6ntkXecO54WWNPVK8avO/2P6aesHfLF8IB2QfD948PV EADAnlJmSPhX+tEQhz4zbZ2svvY4iPIBla84oqKfxSbGYfiFGOk7gw3V/SFi2GCdlSrl dx552N8XgKrcGG7sQ1SOt08b2S1uuNzIh/Mhcsr7ws/jqimR6k5efRFQ+oFVXp1WmOMY Gl2g4s8LyaMoNZGGJQ5gL3dvm5usR0Z1biWMjmUCK+gKxd88S+sOPywJsMPrunl2yuYw 2beEBf0fX8ImhWPMJ6qM3f2NMebAtVepq+BdWI6157QBHm7rWqknlaqNR11RtG68+d0v woEA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u7-v6si1875783plr.241.2018.02.15.14.36.16; Thu, 15 Feb 2018 14:37:11 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1164530AbeBOPcA (ORCPT + 99 others); Thu, 15 Feb 2018 10:32:00 -0500 Received: from mail.linuxfoundation.org ([140.211.169.12]:56202 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1164491AbeBOPb6 (ORCPT ); Thu, 15 Feb 2018 10:31:58 -0500 Received: from localhost (LFbn-1-12258-90.w90-92.abo.wanadoo.fr [90.92.71.90]) by mail.linuxfoundation.org (Postfix) with ESMTPSA id 316ECF01; Thu, 15 Feb 2018 15:31:58 +0000 (UTC) From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Jayachandran C , Will Deacon , Catalin Marinas , Ard Biesheuvel Subject: [PATCH 4.14 048/195] [Variant 3/Meltdown] arm64: cputype: Add MIDR values for Cavium ThunderX2 CPUs Date: Thu, 15 Feb 2018 16:15:39 +0100 Message-Id: <20180215151708.133706586@linuxfoundation.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180215151705.738773577@linuxfoundation.org> References: <20180215151705.738773577@linuxfoundation.org> User-Agent: quilt/0.65 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 4.14-stable review patch. If anyone has any objections, please let me know. ------------------ From: Jayachandran C Commit 0d90718871fe upstream. Add the older Broadcom ID as well as the new Cavium ID for ThunderX2 CPUs. Signed-off-by: Jayachandran C Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Ard Biesheuvel Signed-off-by: Greg Kroah-Hartman --- arch/arm64/include/asm/cputype.h | 3 +++ 1 file changed, 3 insertions(+) --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -87,6 +87,7 @@ #define CAVIUM_CPU_PART_THUNDERX 0x0A1 #define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2 #define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3 +#define CAVIUM_CPU_PART_THUNDERX2 0x0AF #define BRCM_CPU_PART_VULCAN 0x516 @@ -100,6 +101,8 @@ #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) +#define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2) +#define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN) #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1) #define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR) #define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)