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[209.132.180.67]) by mx.google.com with ESMTP id 43-v6si1365110pla.70.2018.02.16.06.58.08; Fri, 16 Feb 2018 06:58:23 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755612AbeBOUYw (ORCPT + 99 others); Thu, 15 Feb 2018 15:24:52 -0500 Received: from Galois.linutronix.de ([146.0.238.70]:55168 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751851AbeBOUYv (ORCPT ); Thu, 15 Feb 2018 15:24:51 -0500 Received: from p4fea5f09.dip0.t-ipconnect.de ([79.234.95.9] helo=nanos.glx-home) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1emQ27-0006uT-7i; Thu, 15 Feb 2018 21:21:31 +0100 Date: Thu, 15 Feb 2018 21:24:56 +0100 (CET) From: Thomas Gleixner To: Lina Iyer cc: jason@lakedaemon.net, marc.zyngier@arm.com, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, asathyak@codeaurora.org Subject: Re: [PATCH v6 1/2] drivers: irqchip: pdc: Add PDC interrupt controller for QCOM SoCs In-Reply-To: <20180215202141.GC23714@codeaurora.org> Message-ID: References: <20180209165735.19151-1-ilina@codeaurora.org> <20180209165735.19151-2-ilina@codeaurora.org> <20180215202141.GC23714@codeaurora.org> User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 15 Feb 2018, Lina Iyer wrote: > On Mon, Feb 12 2018 at 13:40 +0000, Thomas Gleixner wrote: > > On Fri, 9 Feb 2018, Lina Iyer wrote: > > > +enum pdc_irq_config_bits { > > > + PDC_POLARITY_LOW = 0, > > > + PDC_FALLING_EDGE = 2, > > > + PDC_POLARITY_HIGH = 4, > > > + PDC_RISING_EDGE = 6, > > > + PDC_DUAL_EDGE = 7, > > > > My previous comment about using binary constants still stands. Please > > either address review comments or reply at least. Ignoring reviews is not > > an option. > > > > Aside of that I really have to ask about the naming of these constants. Are > > these names hardware register nomenclature? If yes, they are disgusting. If > > no, they are still disgusting, but should be changed to sensible ones, > > which just match the IRQ_TYPE naming convention. > > > > PDC_LEVEL_LOW = 000b, > > PDC_EDGE_FALLING = 010b, > > .... > > > > > Checkpatch doesn't like binary constants. I guess I will need to keep > the enum definitions in hex or decimal. I will remove the binary from > the comments though. Well checkpatch is not always right. > > commit 95e2c6023b0e4c8499fb521697f79215f69135fe > Author: Joe Perches > Date: Wed Jul 3 15:05:20 2013 -0700 > > checkpatch: warn when using gcc's binary constant ("0b") extension > > The gcc extension for binary constants that start with 0b is only > supported with gcc version 4.3 or higher. Can anything of this be compiled with gcc < 4.3? Thanks, tglx