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[209.132.180.67]) by mx.google.com with ESMTP id y20-v6si1284917pll.773.2018.02.16.08.47.38; Fri, 16 Feb 2018 08:47:53 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1161780AbeBOTyM (ORCPT + 99 others); Thu, 15 Feb 2018 14:54:12 -0500 Received: from mail.kernel.org ([198.145.29.99]:54894 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1161559AbeBOTx6 (ORCPT ); Thu, 15 Feb 2018 14:53:58 -0500 Received: from mail-it0-f48.google.com (mail-it0-f48.google.com [209.85.214.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 96EE8217C0 for ; Thu, 15 Feb 2018 19:53:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 96EE8217C0 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=luto@kernel.org Received: by mail-it0-f48.google.com with SMTP id 140so1786816iti.0 for ; Thu, 15 Feb 2018 11:53:57 -0800 (PST) X-Gm-Message-State: APf1xPDW9ZZAtQslvSeWs9sHr4ClXoLqOCA4+2VGvrNzNVc7YyCisJ5b tFLD0sP2ZZDYkzMRW25gRmTVwS07/y0UuYKd095pPQ== X-Received: by 10.36.1.20 with SMTP id 20mr5146468itk.104.1518724437014; Thu, 15 Feb 2018 11:53:57 -0800 (PST) MIME-Version: 1.0 Received: by 10.2.137.84 with HTTP; Thu, 15 Feb 2018 11:53:36 -0800 (PST) In-Reply-To: <20180215163602.61162-6-namit@vmware.com> References: <20180215163602.61162-1-namit@vmware.com> <20180215163602.61162-6-namit@vmware.com> From: Andy Lutomirski Date: Thu, 15 Feb 2018 19:53:36 +0000 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH RFC v2 5/6] x86: Use global pages when PTI is disabled To: Nadav Amit Cc: Ingo Molnar , Thomas Gleixner , Andy Lutomirski , Peter Zijlstra , Dave Hansen , Willy Tarreau , Nadav Amit , X86 ML , LKML Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Feb 15, 2018 at 4:36 PM, Nadav Amit wrote: > As long as PTI is disabled, it is possible to use global pages, as long > as we remove them once PTI is enabled again. To do so, return the global > bit to __supported_pte_mask and disable global pages using CR4. > > Signed-off-by: Nadav Amit > --- > arch/x86/include/asm/tlbflush.h | 6 ++++++ > arch/x86/mm/init.c | 14 ++++++-------- > arch/x86/mm/tlb.c | 3 ++- > 3 files changed, 14 insertions(+), 9 deletions(-) > > diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h > index ea65cf951c49..3a44cb0a9f56 100644 > --- a/arch/x86/include/asm/tlbflush.h > +++ b/arch/x86/include/asm/tlbflush.h > @@ -319,6 +319,12 @@ static inline void set_cpu_pti_disable(unsigned short disable) > WARN_ON_ONCE(preemptible()); > > pti_update_user_cs64(cpu_pti_disable(), disable); > + if (__supported_pte_mask & _PAGE_GLOBAL) { > + if (disable) > + cr4_set_bits(X86_CR4_PGE); > + else > + cr4_clear_bits(X86_CR4_PGE); > + } This will be *extremely* slow, and I don't see the point at all. What are you accomplishing here? At best, you might gain something by adjusting the page table entries to get globalness back, but I see no reason to fiddle with CR4. Also, if you do any of this at all and you run on K8, you're at risk of getting machine checks unless you're very careful to get the invalidation right. I would just drop this patch, personally.