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[209.132.180.67]) by mx.google.com with ESMTP id j186si2326164pgc.175.2018.02.16.09.36.08; Fri, 16 Feb 2018 09:36:23 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=Jj5LLaQQ; dkim=pass header.i=@codeaurora.org header.s=default header.b=Jj5LLaQQ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755987AbeBOV1u (ORCPT + 99 others); Thu, 15 Feb 2018 16:27:50 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:37498 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755948AbeBOV1t (ORCPT ); Thu, 15 Feb 2018 16:27:49 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id BC4C560F6D; Thu, 15 Feb 2018 21:27:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1518730068; bh=6erReDbDzemOeQm/Mk61wf0lbMlTxilrQy8HPZU7XB4=; h=From:To:Cc:Subject:Date:From; b=Jj5LLaQQaeHrPedeYPzYyzQHjFovT6NC9CWutA//DGURY9tBTXD6d8oCnsW5G0zae q2X5pEUfo8wVB5QVGaCEq8/i+mbKCKaM5VdsuZCp6rAxz/ugDINO4MV+iQgMT93U9s fZZOfKOlEWPUvltHI0NY75eT9XcxM45RvOMfb4rA= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id AEE8F60960; Thu, 15 Feb 2018 21:27:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1518730068; bh=6erReDbDzemOeQm/Mk61wf0lbMlTxilrQy8HPZU7XB4=; h=From:To:Cc:Subject:Date:From; b=Jj5LLaQQaeHrPedeYPzYyzQHjFovT6NC9CWutA//DGURY9tBTXD6d8oCnsW5G0zae q2X5pEUfo8wVB5QVGaCEq8/i+mbKCKaM5VdsuZCp6rAxz/ugDINO4MV+iQgMT93U9s fZZOfKOlEWPUvltHI0NY75eT9XcxM45RvOMfb4rA= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org AEE8F60960 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rnayak@codeaurora.org, asathyak@codeaurora.org, Lina Iyer Subject: [PATCH v7 0/2] irqchip: qcom: add support for PDC interrupt controller Date: Thu, 15 Feb 2018 14:27:40 -0700 Message-Id: <20180215212742.4675-1-ilina@codeaurora.org> X-Mailer: git-send-email 2.16.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Changes since v6: - Code clean up as suggested by Thomas - Rebased on top of 4.16-rc1 On newer Qualcomm Techonologies Inc's SoCs like the SDM845, the GIC is in a power domain that can be powered off when not needed. Interrupts that need to be sensed even when the GIC is powered off, are routed through an interrupt controller in an always-on domain called the Power Domain Controller a.k.a PDC. This series adds support for the PDC's interrupt controller. Please consider reviewing these patches. RFC v1: https://patchwork.kernel.org/patch/10180857/ RFC v2: https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1600634.html v3: https://lkml.org/lkml/2018/2/6/595 v4: https://www.spinics.net/lists/linux-arm-msm/msg32906.html v5: https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1605500.html v6: https://lkml.org/lkml/2018/2/9/545 Lina Iyer (2): drivers: irqchip: pdc: Add PDC interrupt controller for QCOM SoCs dt-bindings/interrupt-controller: pdc: describe PDC device binding .../bindings/interrupt-controller/qcom,pdc.txt | 78 ++++++ drivers/irqchip/Kconfig | 9 + drivers/irqchip/Makefile | 1 + drivers/irqchip/qcom-pdc.c | 311 +++++++++++++++++++++ 4 files changed, 399 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt create mode 100644 drivers/irqchip/qcom-pdc.c -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project