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[209.132.180.67]) by mx.google.com with ESMTP id b3si3025416pgc.496.2018.02.16.10.53.32; Fri, 16 Feb 2018 10:53:47 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=jsWRL9Wi; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932094AbeBPJg0 (ORCPT + 99 others); Fri, 16 Feb 2018 04:36:26 -0500 Received: from mail-qt0-f195.google.com ([209.85.216.195]:35581 "EHLO mail-qt0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932071AbeBPJgY (ORCPT ); Fri, 16 Feb 2018 04:36:24 -0500 Received: by mail-qt0-f195.google.com with SMTP id g14so3044774qti.2; Fri, 16 Feb 2018 01:36:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=4vIVWwjp0L8i1AcW1b6OHmUb9wtJALJw1IQ+iSImAC0=; b=jsWRL9WiKiUtYpkbmFYJrxw0/oIYK3zWOf1yu3RpY4M4X2ok4Zox/Gs4vUVnGsNwkl UwUd4/k515pfc6LI33tHhOr6odndYk11P7vCxvYpCyTBZaweF8N1ThDjeDXoW4Vlgeks 8fj2BA/rF3e6H5tQpmGOLL7okwJQUUPo5nlaQFB8kpeeUxReIpbEpxK4opsRHIiVg8Ar tQ1gZsewLPceTv/ysPxdQTUBjwennGIg1KZrmtm0HW+pZsWhtQrNR7CRuOq0eDXtISzO p8N+32qnM7ycKJS1V/ZQciG3MApkjVuZc3CsGdSuS07h0D8fWl7CMVATe3+QimSchnbP NniA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:sender:in-reply-to:references:from :date:message-id:subject:to:cc; bh=4vIVWwjp0L8i1AcW1b6OHmUb9wtJALJw1IQ+iSImAC0=; b=OYVV0y3bbt3R8IheX/+CQBexMzKJbxhOKxWbvqs7cXgO680cfjjGNYD2cBuVnBRQ/D GVytD1t8oeD8fhMyl1xjE1xYrFIdLryK2XLaSXfiiSqjGf4VTed+09i89BmIzi0b08LI 8+PLJCLbf5OiUSyd/alN1nSGdnraRJ3BvUepoyCJpLsrxZXGFKJMaHj8a3/5FWNmdhWS 0nhdvAoPL80bOAN7ueypvOmE+hQDw3N3sEOqF+4xi0GsDcV4rylJ4kXEkcus6WLXgD2a XPtjnA2XKiWZxA1N+//WlpgNPQ2SDn9HK3JHtw8mVhpP9ocx+x+oG+PN1OhYCiPRQJUt /LyA== X-Gm-Message-State: APf1xPDT2lrP+ZvgQXgZwU4t00ZSaO1oygs1oAr1BUrudt6w6vRcpU3x /8BdgP6sYw9XXsVNVuusVhezmzjcd7AUY8lmrl4= X-Received: by 10.237.36.110 with SMTP id s43mr8963634qtc.23.1518773783683; Fri, 16 Feb 2018 01:36:23 -0800 (PST) MIME-Version: 1.0 Received: by 10.200.47.219 with HTTP; Fri, 16 Feb 2018 01:36:23 -0800 (PST) In-Reply-To: <1518515162-23663-6-git-send-email-jacopo+renesas@jmondi.org> References: <1518515162-23663-1-git-send-email-jacopo+renesas@jmondi.org> <1518515162-23663-6-git-send-email-jacopo+renesas@jmondi.org> From: Geert Uytterhoeven Date: Fri, 16 Feb 2018 10:36:23 +0100 X-Google-Sender-Auth: JWXj0bu2iNv5BCPpb718W80SaLk Message-ID: Subject: Re: [PATCH 05/15] ARM64: dts: Add R-Car Salvator-x M3-N support To: Jacopo Mondi Cc: Simon Horman , Magnus Damm , Rob Herring , Mark Rutland , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-arm-kernel@lists.infradead.org, Linux-Renesas , Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jacopo, On Tue, Feb 13, 2018 at 10:45 AM, Jacopo Mondi wrote: > Add initial support for R-Car M3-N Salvator-x and r8a77965 SoC in > device tree with cpg-mssr, reset and clock nodes. > > Add place-holder device nodes for all nodes referred by > "salvator-common.dtsi" > > Signed-off-by: Jacopo Mondi > --- /dev/null > +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi > + gic: interrupt-controller@f1010000 { > + compatible = "arm,gic-400"; > + #interrupt-cells = <3>; > + #address-cells = <0>; > + interrupt-controller; > + reg = <0x0 0xf1010000 0 0x1000>, > + <0x0 0xf1020000 0 0x20000>, > + <0x0 0xf1040000 0 0x20000>, > + <0x0 0xf1060000 0 0x20000>; > + interrupts = + (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; Given you have 2 CPU cores, it should say GIC_CPU_MASK_SIMPLE(2). > + clocks = <&cpg CPG_MOD 408>; > + clock-names = "clk"; > + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; > + resets = <&cpg 408>; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, > + + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, > + + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, > + + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; This one is correct. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds