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Message-ID: <1518776517.7876.21.camel@infradead.org>
Subject: Re: [PATCH 2/2] x86/speculation: Support "Enhanced IBRS" on future
 CPUs
From:   David Woodhouse <dwmw2@infradead.org>
To:     Paolo Bonzini <pbonzini@redhat.com>, tglx@linutronix.de,
        x86@kernel.org, kvm@vger.kernel.org, torvalds@linux-foundation.org,
        linux-kernel@vger.kernel.org, arjan.van.de.ven@intel.com,
        dave.hansen@intel.com
Cc:     Ingo Molnar <mingo@kernel.org>
In-Reply-To: <75287047-77a0-e0ff-c2e8-61c81641251e@redhat.com>
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Date:   Fri, 16 Feb 2018 10:21:57 +0000
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On Fri, 2018-02-16 at 11:08 +0100, Paolo Bonzini wrote:
> On 16/02/2018 10:58, David Woodhouse wrote:
> >=20
> > On Tue, 2018-02-13 at 11:41 +0100, Paolo Bonzini wrote:
> >=20
> > >=20
> > > On 13/02/2018 11:36, David Woodhouse wrote:
> > > >=20
> > > > >=20
> > > > > >=20
> > > > > > - if the VM has IBRS_ALL, pass through the MSR when it is zero =
and
> > > > > > intercept writes when it is one (no writes should happen)
> > > > > > =C2=A0
> > > > > > - if the VM doesn't have IBRS_ALL, do as we are doing now, inde=
pendent
> > > > > > of what the host spectre_v2_ibrs_all() setting is.
> > > > > We end up having to turn IBRS on again on vmexit then, taking car=
e that
> > > > > no conditional branch can go round it. So that becomes an
> > > > > *unconditional* wrmsr or lfence in the vmexit path. We really don=
't
> > > > > want that.
> > > > >=20
> > > > Note that being able to keep it simple in KVM was basically what ma=
de
> > > > the difference between me tolerating IBRS_ALL as Intel currently de=
fine
> > > > it, and throwing my toys out of the pram (as I had done in the firs=
t
> > > > iterations of this patch).
> > > =C2=A0
> > > You have my vote. :)
> >=20
> > I was taking that as assent to the patch... could I trouble you for an
> > explicit ack, please?
>
> No, it's a vote for throwing the toys out of the pram (or running away
> with the ball, if you prefer).
>=20
> Unfortunately, if you want to have a higher-performance mode for
> IBRS_ALL that avoids rdmsr on vmexit, you have to do it as sketched above=
.


Why? With IBRS_ALL the guest *never* gets to affect the actual hardware
MSR, which is always on. The MSR is purely an emulated no-op. Why does
that affect migration?

Even if the guest doesn't have/support IBRS_ALL, and is frobbing the
(now emulated) MSR on every kernel entry/exit, that's *still* going to
be a metric shitload faster than what it *thought* it was doing.

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